{"id":"https://openalex.org/W1999976875","doi":"https://doi.org/10.1016/0167-9260(93)90056-i","title":"A language for designer controlled behavioral synthesis","display_name":"A language for designer controlled behavioral synthesis","publication_year":1993,"publication_date":"1993-11-01","ids":{"openalex":"https://openalex.org/W1999976875","doi":"https://doi.org/10.1016/0167-9260(93)90056-i","mag":"1999976875"},"language":"en","primary_location":{"id":"doi:10.1016/0167-9260(93)90056-i","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(93)90056-i","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007817952","display_name":"Nikil Dutt","orcid":"https://orcid.org/0000-0002-3060-8119"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nikil D. Dutt","raw_affiliation_strings":["Department of Information & Computer Science, University of California at Irvine, Irvine, CA 92717-3425, USA"],"affiliations":[{"raw_affiliation_string":"Department of Information & Computer Science, University of California at Irvine, Irvine, CA 92717-3425, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5007817952"],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14269142,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":"1","first_page":"1","last_page":"31"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8118208646774292},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7668282985687256},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.721848726272583},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6935297250747681},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.641289234161377},{"id":"https://openalex.org/keywords/language-construct","display_name":"Language construct","score":0.5213345289230347},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5130630731582642},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5082852244377136},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4731888771057129},{"id":"https://openalex.org/keywords/specification-language","display_name":"Specification language","score":0.4548793435096741},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43652987480163574},{"id":"https://openalex.org/keywords/design-language","display_name":"Design language","score":0.4287464916706085},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3756147623062134},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21547859907150269},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1849653720855713}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8118208646774292},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7668282985687256},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.721848726272583},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6935297250747681},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.641289234161377},{"id":"https://openalex.org/C48859967","wikidata":"https://www.wikidata.org/wiki/Q6486712","display_name":"Language construct","level":2,"score":0.5213345289230347},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5130630731582642},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5082852244377136},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4731888771057129},{"id":"https://openalex.org/C201677973","wikidata":"https://www.wikidata.org/wiki/Q1209840","display_name":"Specification language","level":2,"score":0.4548793435096741},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43652987480163574},{"id":"https://openalex.org/C49777639","wikidata":"https://www.wikidata.org/wiki/Q5264354","display_name":"Design language","level":2,"score":0.4287464916706085},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3756147623062134},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21547859907150269},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1849653720855713},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0167-9260(93)90056-i","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(93)90056-i","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":46,"referenced_works":["https://openalex.org/W756394636","https://openalex.org/W1483234693","https://openalex.org/W1500142795","https://openalex.org/W1513250879","https://openalex.org/W1567363020","https://openalex.org/W1573733217","https://openalex.org/W1968782742","https://openalex.org/W1977298531","https://openalex.org/W2002209544","https://openalex.org/W2014984434","https://openalex.org/W2026146545","https://openalex.org/W2028971136","https://openalex.org/W2042202727","https://openalex.org/W2043256264","https://openalex.org/W2069295582","https://openalex.org/W2087376924","https://openalex.org/W2100038922","https://openalex.org/W2101011466","https://openalex.org/W2101776637","https://openalex.org/W2104932323","https://openalex.org/W2105205741","https://openalex.org/W2109507516","https://openalex.org/W2114087158","https://openalex.org/W2118087925","https://openalex.org/W2118387410","https://openalex.org/W2119440680","https://openalex.org/W2142403965","https://openalex.org/W2156807022","https://openalex.org/W2167614122","https://openalex.org/W2319391015","https://openalex.org/W3008482905","https://openalex.org/W3010647366","https://openalex.org/W3011532250","https://openalex.org/W3109454929","https://openalex.org/W6629030970","https://openalex.org/W6634438343","https://openalex.org/W6661159975","https://openalex.org/W6674987496","https://openalex.org/W6675040252","https://openalex.org/W6675757881","https://openalex.org/W6676916114","https://openalex.org/W6677498807","https://openalex.org/W6678156753","https://openalex.org/W6774037378","https://openalex.org/W6774493671","https://openalex.org/W6775412097"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2147198083","https://openalex.org/W2384838054","https://openalex.org/W2075214143","https://openalex.org/W2389325540","https://openalex.org/W2388371416","https://openalex.org/W4236484345","https://openalex.org/W2109177648","https://openalex.org/W2204921341"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
