{"id":"https://openalex.org/W2041510221","doi":"https://doi.org/10.1016/0167-9260(92)90029-x","title":"Synthesis and self-test of random logic control units","display_name":"Synthesis and self-test of random logic control units","publication_year":1992,"publication_date":"1992-09-01","ids":{"openalex":"https://openalex.org/W2041510221","doi":"https://doi.org/10.1016/0167-9260(92)90029-x","mag":"2041510221"},"language":"en","primary_location":{"id":"doi:10.1016/0167-9260(92)90029-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(92)90029-x","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074307451","display_name":"Bernhard Eschermann","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Bernhard Eschermann","raw_affiliation_strings":["Universit\u00e4t-GH-Siegen, FB 12-Rechnerstrukturen, H\u00f6lderlinstra\u03b2e 3, 5900 Siegen, Germany"],"affiliations":[{"raw_affiliation_string":"Universit\u00e4t-GH-Siegen, FB 12-Rechnerstrukturen, H\u00f6lderlinstra\u03b2e 3, 5900 Siegen, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5074307451"],"corresponding_institution_ids":[],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":0.3788,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.64912281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"13","issue":"3","first_page":"209","last_page":"230"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9842000007629395,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.984000027179718,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.687333881855011},{"id":"https://openalex.org/keywords/signature","display_name":"Signature (topology)","score":0.6263397932052612},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6059491038322449},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5944758653640747},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.5808861255645752},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5400662422180176},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5115726590156555},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.47480905055999756},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4678386449813843},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44132593274116516},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.43595778942108154},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39214199781417847},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37515032291412354},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.27820873260498047},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2664344608783722},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2207610011100769},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.16580235958099365},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12008577585220337},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07048311829566956}],"concepts":[{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.687333881855011},{"id":"https://openalex.org/C2779696439","wikidata":"https://www.wikidata.org/wiki/Q7512811","display_name":"Signature (topology)","level":2,"score":0.6263397932052612},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6059491038322449},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5944758653640747},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.5808861255645752},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5400662422180176},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5115726590156555},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.47480905055999756},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4678386449813843},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44132593274116516},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.43595778942108154},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39214199781417847},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37515032291412354},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27820873260498047},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2664344608783722},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2207610011100769},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.16580235958099365},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12008577585220337},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07048311829566956},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0167-9260(92)90029-x","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(92)90029-x","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W327215","https://openalex.org/W1541660094","https://openalex.org/W1581405316","https://openalex.org/W1952162104","https://openalex.org/W1965850601","https://openalex.org/W1995595470","https://openalex.org/W2004463345","https://openalex.org/W2034279552","https://openalex.org/W2081272455","https://openalex.org/W2082909013","https://openalex.org/W2096667381","https://openalex.org/W2101492865","https://openalex.org/W2111151532","https://openalex.org/W2116314988","https://openalex.org/W2118330187","https://openalex.org/W2123900388","https://openalex.org/W2133663422","https://openalex.org/W2144083417","https://openalex.org/W2144947360","https://openalex.org/W2148830996","https://openalex.org/W2152870025","https://openalex.org/W2159653476","https://openalex.org/W2171795575","https://openalex.org/W2751862591","https://openalex.org/W3118259273","https://openalex.org/W4241000183","https://openalex.org/W6632577423","https://openalex.org/W6634808979","https://openalex.org/W6640649184","https://openalex.org/W6651576451","https://openalex.org/W6675379061","https://openalex.org/W6681600634","https://openalex.org/W6683632498"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2168652618","https://openalex.org/W776711554","https://openalex.org/W4245595174","https://openalex.org/W2115513740","https://openalex.org/W2539511314","https://openalex.org/W2150335661"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}