{"id":"https://openalex.org/W1994376444","doi":"https://doi.org/10.1016/0167-9260(91)90048-p","title":"Formally verified synthesis of combinational CMOS circuits","display_name":"Formally verified synthesis of combinational CMOS circuits","publication_year":1991,"publication_date":"1991-06-01","ids":{"openalex":"https://openalex.org/W1994376444","doi":"https://doi.org/10.1016/0167-9260(91)90048-p","mag":"1994376444"},"language":"en","primary_location":{"id":"doi:10.1016/0167-9260(91)90048-p","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(91)90048-p","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025344654","display_name":"David Basin","orcid":"https://orcid.org/0000-0003-2952-939X"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]},{"id":"https://openalex.org/I4210109712","display_name":"Max Planck Institute for Informatics","ror":"https://ror.org/01w19ak89","country_code":"DE","type":"facility","lineage":["https://openalex.org/I149899117","https://openalex.org/I4210109712"]},{"id":"https://openalex.org/I149899117","display_name":"Max Planck Society","ror":"https://ror.org/01hhn8329","country_code":"DE","type":"funder","lineage":["https://openalex.org/I149899117"]}],"countries":["DE","GB"],"is_corresponding":true,"raw_author_name":"David A. Basin","raw_affiliation_strings":["Department of Computer Science, University of Edinburgh, The King's Bldg, Edinburgh EH9 3JK, UK","Programming Logics, MPI for Informatics, Max Planck Society"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Edinburgh, The King's Bldg, Edinburgh EH9 3JK, UK","institution_ids":["https://openalex.org/I98677209"]},{"raw_affiliation_string":"Programming Logics, MPI for Informatics, Max Planck Society","institution_ids":["https://openalex.org/I4210109712","https://openalex.org/I149899117"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103464606","display_name":"Geoffrey Brown","orcid":"https://orcid.org/0009-0004-6180-7673"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Geoffrey M. Brown","raw_affiliation_strings":["School of Electrical Engeering, Cornell University, Ithaca, NY 14853, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engeering, Cornell University, Ithaca, NY 14853, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083047329","display_name":"Miriam Leeser","orcid":"https://orcid.org/0000-0002-5624-056X"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Miriam E. Leeser","raw_affiliation_strings":["School of Electrical Engeering, Cornell University, Ithaca, NY 14853, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engeering, Cornell University, Ithaca, NY 14853, USA","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5025344654"],"corresponding_institution_ids":["https://openalex.org/I149899117","https://openalex.org/I4210109712","https://openalex.org/I98677209"],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":1.5394,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.80748798,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":"3","first_page":"235","last_page":"250"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7582056522369385},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.727756142616272},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6496778130531311},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5914888978004456},{"id":"https://openalex.org/keywords/transformation","display_name":"Transformation (genetics)","score":0.5830020904541016},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48591628670692444},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.45026707649230957},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4165908098220825},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3750240206718445},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3635738492012024},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.26790860295295715},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24777477979660034},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22738605737686157},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13266053795814514},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12548455595970154}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7582056522369385},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.727756142616272},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6496778130531311},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5914888978004456},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.5830020904541016},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48591628670692444},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.45026707649230957},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4165908098220825},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3750240206718445},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3635738492012024},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.26790860295295715},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24777477979660034},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22738605737686157},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13266053795814514},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12548455595970154},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0167-9260(91)90048-p","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(91)90048-p","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},{"id":"pmh:oai:escidoc.org:escidoc:2048499","is_oa":false,"landing_page_url":"http://hdl.handle.net/11858/00-001M-0000-001A-2593-9","pdf_url":null,"source":{"id":"https://openalex.org/S7407052962","display_name":"Max Planck Digital Library","issn_l":null,"issn":[],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W17786439","https://openalex.org/W1140735603","https://openalex.org/W1527057751","https://openalex.org/W1546202437","https://openalex.org/W1585234943","https://openalex.org/W1636139685","https://openalex.org/W1725493355","https://openalex.org/W1978847232","https://openalex.org/W1993847066","https://openalex.org/W2006097283","https://openalex.org/W2072110970","https://openalex.org/W2089448146","https://openalex.org/W2105761964","https://openalex.org/W2106718208","https://openalex.org/W2106918565","https://openalex.org/W2128057448","https://openalex.org/W2157028115","https://openalex.org/W2168491240","https://openalex.org/W4248066563","https://openalex.org/W4250956016","https://openalex.org/W6600725135","https://openalex.org/W6627148737","https://openalex.org/W6632814518","https://openalex.org/W6637625336","https://openalex.org/W6668459822","https://openalex.org/W6673018402","https://openalex.org/W6676111922","https://openalex.org/W6676279763","https://openalex.org/W6678950827","https://openalex.org/W6683191781"],"related_works":["https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W2163776294","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W4390345338"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
