{"id":"https://openalex.org/W2058935377","doi":"https://doi.org/10.1016/0167-9260(89)90036-9","title":"An enhanced bottom-up algorithm for floorplan design","display_name":"An enhanced bottom-up algorithm for floorplan design","publication_year":1989,"publication_date":"1989-08-01","ids":{"openalex":"https://openalex.org/W2058935377","doi":"https://doi.org/10.1016/0167-9260(89)90036-9","mag":"2058935377"},"language":"en","primary_location":{"id":"doi:10.1016/0167-9260(89)90036-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(89)90036-9","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103607635","display_name":"Thomas R. Mueller","orcid":null},"institutions":[{"id":"https://openalex.org/I176714629","display_name":"Bell (Canada)","ror":"https://ror.org/00xdg8m59","country_code":"CA","type":"company","lineage":["https://openalex.org/I176714629"]},{"id":"https://openalex.org/I72090969","display_name":"Nokia (United States)","ror":"https://ror.org/038km2573","country_code":"US","type":"company","lineage":["https://openalex.org/I2738502077","https://openalex.org/I72090969"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"Thomas R. Mueller","raw_affiliation_strings":["AT&T Bell Laboratories, Naperville, IL 60566 U.S.A","AT&T Bell Laboratories, Naperville, IL#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"AT&T Bell Laboratories, Naperville, IL 60566 U.S.A","institution_ids":["https://openalex.org/I176714629"]},{"raw_affiliation_string":"AT&T Bell Laboratories, Naperville, IL#TAB#","institution_ids":["https://openalex.org/I72090969"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053378706","display_name":"Martin D. F. Wong","orcid":"https://orcid.org/0000-0001-8274-9688"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.F. Wong","raw_affiliation_strings":["Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712, U.S.A","University of Texas at Austin, Austin"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712, U.S.A","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"University of Texas at Austin, Austin","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110923944","display_name":"C. L. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.L. Liu","raw_affiliation_strings":["Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, U.S.A","University of Illinois at Urbana-Champaign Urbana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801, U.S.A","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"University of Illinois at Urbana-Champaign Urbana","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":1.9932,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.85343342,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"2","first_page":"189","last_page":"201"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9905925393104553},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.8476110100746155},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.6322346925735474},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5090076923370361},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.44394010305404663},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3329582214355469},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.20782199501991272},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12866607308387756}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9905925393104553},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.8476110100746155},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.6322346925735474},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5090076923370361},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.44394010305404663},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3329582214355469},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.20782199501991272},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12866607308387756},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0167-9260(89)90036-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(89)90036-9","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1655990431","https://openalex.org/W1986679986","https://openalex.org/W2065838697","https://openalex.org/W2094042791","https://openalex.org/W2110514755","https://openalex.org/W6646928167","https://openalex.org/W6674301526","https://openalex.org/W6676972468"],"related_works":["https://openalex.org/W3015761757","https://openalex.org/W96081925","https://openalex.org/W2102616729","https://openalex.org/W2117901445","https://openalex.org/W2261987718","https://openalex.org/W4256007160","https://openalex.org/W2094042791","https://openalex.org/W4205135025","https://openalex.org/W3153286430","https://openalex.org/W1535529518"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
