{"id":"https://openalex.org/W2036915331","doi":"https://doi.org/10.1016/0167-9260(89)90005-9","title":"Selecting test methodologies for PLAs and random logic modules in VLSI circuits \u2014 an expert systems approach","display_name":"Selecting test methodologies for PLAs and random logic modules in VLSI circuits \u2014 an expert systems approach","publication_year":1989,"publication_date":"1989-09-01","ids":{"openalex":"https://openalex.org/W2036915331","doi":"https://doi.org/10.1016/0167-9260(89)90005-9","mag":"2036915331"},"language":"en","primary_location":{"id":"doi:10.1016/0167-9260(89)90005-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(89)90005-9","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069773943","display_name":"Sudipta Bhawmik","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudipta Bhawmik","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","Indian Institute of Technology, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112944450","display_name":"V. Narang","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V.K. Narang","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","Indian Institute of Technology, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108336757","display_name":"Parimal Pal Chaudhuri","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Parimal Pal Chaudhuri","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","Indian Institute of Technology, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721302, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2150,"currency":"USD","value_usd":2150},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.17074182,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"3","first_page":"267","last_page":"281"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5971654057502747},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5748562812805176},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5623656511306763},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.537661612033844},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.506121814250946},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4895339906215668},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.46970388293266296},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4601576328277588},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.43377673625946045},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41606128215789795},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3996945023536682},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3863930106163025},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36687833070755005},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.33113962411880493},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3159428834915161},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25280123949050903},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2416822910308838},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1257067620754242}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5971654057502747},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5748562812805176},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5623656511306763},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.537661612033844},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.506121814250946},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4895339906215668},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.46970388293266296},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4601576328277588},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.43377673625946045},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41606128215789795},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3996945023536682},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3863930106163025},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36687833070755005},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.33113962411880493},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3159428834915161},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25280123949050903},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2416822910308838},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1257067620754242},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0167-9260(89)90005-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-9260(89)90005-9","pdf_url":null,"source":{"id":"https://openalex.org/S139392130","display_name":"Integration","issn_l":"0167-9260","issn":["0167-9260","1872-7522"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integration","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W30991368","https://openalex.org/W1845681645","https://openalex.org/W1988556782","https://openalex.org/W2014414135","https://openalex.org/W2029173745","https://openalex.org/W2034476614","https://openalex.org/W2044076967","https://openalex.org/W2055327461","https://openalex.org/W2055575506","https://openalex.org/W2078888330","https://openalex.org/W2109678242","https://openalex.org/W2133222590","https://openalex.org/W4205958155","https://openalex.org/W6664318521","https://openalex.org/W6676363538"],"related_works":["https://openalex.org/W2120257283","https://openalex.org/W2117563988","https://openalex.org/W2161696808","https://openalex.org/W4240466429","https://openalex.org/W1579528621","https://openalex.org/W2141620082","https://openalex.org/W2140497172","https://openalex.org/W2168652618","https://openalex.org/W2127247647","https://openalex.org/W2166402441"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}