{"id":"https://openalex.org/W2016076352","doi":"https://doi.org/10.1016/0167-8191(93)90047-o","title":"A parallel system for test pattern generation","display_name":"A parallel system for test pattern generation","publication_year":1993,"publication_date":"1993-02-01","ids":{"openalex":"https://openalex.org/W2016076352","doi":"https://doi.org/10.1016/0167-8191(93)90047-o","mag":"2016076352"},"language":"en","primary_location":{"id":"doi:10.1016/0167-8191(93)90047-o","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-8191(93)90047-o","pdf_url":null,"source":{"id":"https://openalex.org/S112708030","display_name":"Parallel Computing","issn_l":"0167-8191","issn":["0167-8191","1872-7336"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081884180","display_name":"Gian Paolo Balboni","orcid":null},"institutions":[{"id":"https://openalex.org/I1298633626","display_name":"Telecom Italia Lab","ror":"https://ror.org/01rt74q71","country_code":"IT","type":"facility","lineage":["https://openalex.org/I1298633626","https://openalex.org/I137543953"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G.P Balboni","raw_affiliation_strings":["CSELT, Centro Studi e Laboratori Telecomunicazioni SpA, via G. Reiss Romoli 274, I-10148, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"CSELT, Centro Studi e Laboratori Telecomunicazioni SpA, via G. Reiss Romoli 274, I-10148, Torino, Italy","institution_ids":["https://openalex.org/I1298633626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075485175","display_name":"Gianpiero Cabodi","orcid":"https://orcid.org/0000-0001-5839-8697"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G.P Cabodi","raw_affiliation_strings":["Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032806691","display_name":"Shan Gai","orcid":"https://orcid.org/0000-0001-6139-1410"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"S Gai","raw_affiliation_strings":["Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M Sonza Reorda","raw_affiliation_strings":["Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Politecnico di Torino, Dip. Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5058555274"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":{"value":2680,"currency":"USD","value_usd":2680},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15113278,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"19","issue":"2","first_page":"177","last_page":"185"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.8545821905136108},{"id":"https://openalex.org/keywords/transputer","display_name":"Transputer","score":0.8115717768669128},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7682698369026184},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7235388159751892},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6842104196548462},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.6764066219329834},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6213838458061218},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5993548631668091},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.5311578512191772},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5173846483230591},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4910285472869873},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.43601712584495544},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.41495001316070557},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3614501953125},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.29256612062454224},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10468396544456482}],"concepts":[{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.8545821905136108},{"id":"https://openalex.org/C2778319340","wikidata":"https://www.wikidata.org/wiki/Q776861","display_name":"Transputer","level":2,"score":0.8115717768669128},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7682698369026184},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7235388159751892},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6842104196548462},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.6764066219329834},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6213838458061218},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5993548631668091},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.5311578512191772},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5173846483230591},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4910285472869873},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.43601712584495544},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41495001316070557},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3614501953125},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29256612062454224},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10468396544456482},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0167-8191(93)90047-o","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-8191(93)90047-o","pdf_url":null,"source":{"id":"https://openalex.org/S112708030","display_name":"Parallel Computing","issn_l":"0167-8191","issn":["0167-8191","1872-7336"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing","raw_type":"journal-article"},{"id":"pmh:oai:porto.polito.it:1656611","is_oa":false,"landing_page_url":"http://porto.polito.it/1656611/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:0167-8191","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4000000059604645,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W138389420","https://openalex.org/W168622005","https://openalex.org/W1554885925","https://openalex.org/W1566332050","https://openalex.org/W1970112123","https://openalex.org/W1970390910","https://openalex.org/W2015913288","https://openalex.org/W2094165715","https://openalex.org/W2126693329","https://openalex.org/W2149107969","https://openalex.org/W4302458519","https://openalex.org/W6605639199","https://openalex.org/W6606768204","https://openalex.org/W6633738153","https://openalex.org/W6678797189"],"related_works":["https://openalex.org/W2069145203","https://openalex.org/W2085176210","https://openalex.org/W1702800398","https://openalex.org/W2106889348","https://openalex.org/W2083793411","https://openalex.org/W2135500595","https://openalex.org/W2543766998","https://openalex.org/W573124066","https://openalex.org/W1969171031","https://openalex.org/W1592424226"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}