{"id":"https://openalex.org/W3023859623","doi":"https://doi.org/10.1016/0167-8191(90)90125-s","title":"A systolic design for generating combinations in lexicographic order","display_name":"A systolic design for generating combinations in lexicographic order","publication_year":1990,"publication_date":"1990-01-01","ids":{"openalex":"https://openalex.org/W3023859623","doi":"https://doi.org/10.1016/0167-8191(90)90125-s","mag":"3023859623"},"language":"en","primary_location":{"id":"doi:10.1016/0167-8191(90)90125-s","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-8191(90)90125-s","pdf_url":null,"source":{"id":"https://openalex.org/S112708030","display_name":"Parallel Computing","issn_l":"0167-8191","issn":["0167-8191","1872-7336"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110682991","display_name":"J-C. Tsay","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"J.C Tsay","raw_affiliation_strings":["Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan, Republic of China","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103054582","display_name":"Chien\u2010Yu Lin","orcid":"https://orcid.org/0000-0002-0972-9397"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"C.J Lin","raw_affiliation_strings":["Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan, Republic of China"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu, Taiwan, Republic of China","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5110682991"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":{"value":2680,"currency":"USD","value_usd":2680},"apc_paid":null,"fwci":1.0353,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.79396259,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"13","issue":"1","first_page":"119","last_page":"125"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lexicographical-order","display_name":"Lexicographical order","score":0.9167051911354065},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.9022787809371948},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.7371478080749512},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.6784655451774597},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5584109425544739},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5309302806854248},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.499924898147583},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.49115368723869324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47770026326179504},{"id":"https://openalex.org/keywords/order","display_name":"Order (exchange)","score":0.4479213058948517},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4296254515647888},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3708740472793579},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.1537685990333557},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0868186354637146},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.07104998826980591}],"concepts":[{"id":"https://openalex.org/C159254197","wikidata":"https://www.wikidata.org/wiki/Q1144915","display_name":"Lexicographical order","level":2,"score":0.9167051911354065},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.9022787809371948},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7371478080749512},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.6784655451774597},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5584109425544739},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5309302806854248},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.499924898147583},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.49115368723869324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47770026326179504},{"id":"https://openalex.org/C182306322","wikidata":"https://www.wikidata.org/wiki/Q1779371","display_name":"Order (exchange)","level":2,"score":0.4479213058948517},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4296254515647888},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3708740472793579},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.1537685990333557},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0868186354637146},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.07104998826980591},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0167-8191(90)90125-s","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0167-8191(90)90125-s","pdf_url":null,"source":{"id":"https://openalex.org/S112708030","display_name":"Parallel Computing","issn_l":"0167-8191","issn":["0167-8191","1872-7336"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1514415888","https://openalex.org/W1581872756","https://openalex.org/W1586380695","https://openalex.org/W1982762716","https://openalex.org/W2038849941","https://openalex.org/W2050034390","https://openalex.org/W2054388411","https://openalex.org/W2064130185","https://openalex.org/W2073441554","https://openalex.org/W2089000158","https://openalex.org/W2138245082","https://openalex.org/W2148631003","https://openalex.org/W2153514459","https://openalex.org/W2433940709","https://openalex.org/W2494434491","https://openalex.org/W2995746888","https://openalex.org/W3133279294","https://openalex.org/W6666425473","https://openalex.org/W6680419662","https://openalex.org/W6681971441"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W3023859623","https://openalex.org/W2144460576","https://openalex.org/W2091843956","https://openalex.org/W1852653998","https://openalex.org/W2038682752","https://openalex.org/W2142131433","https://openalex.org/W2739720767","https://openalex.org/W2105613219"],"abstract_inverted_index":null,"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
