{"id":"https://openalex.org/W2001840984","doi":"https://doi.org/10.1016/0165-6074(94)90020-5","title":"High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs","display_name":"High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs","publication_year":1994,"publication_date":"1994-12-01","ids":{"openalex":"https://openalex.org/W2001840984","doi":"https://doi.org/10.1016/0165-6074(94)90020-5","mag":"2001840984"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(94)90020-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)90020-5","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040291662","display_name":"A. Antola","orcid":null},"institutions":[{"id":"https://openalex.org/I25217355","display_name":"University of Pavia","ror":"https://ror.org/00s6t1f81","country_code":"IT","type":"education","lineage":["https://openalex.org/I25217355"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Anna Antola","raw_affiliation_strings":["Dipartimento di Informatica e Sistemistica - Universit\u00e0 di Pavia ITALY","Dipartimento di Informatica e Sistemistica, Universit\u00e1 di Pavia, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica e Sistemistica - Universit\u00e0 di Pavia ITALY","institution_ids":["https://openalex.org/I25217355"]},{"raw_affiliation_string":"Dipartimento di Informatica e Sistemistica, Universit\u00e1 di Pavia, Italy","institution_ids":["https://openalex.org/I25217355"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032269174","display_name":"F. Distante","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fausto Distante","raw_affiliation_strings":["Dipartimento di Elettronica ed Informazione - Politecnico di Milano ITALY","Dipartimento di Elettronica ed Informazione - Politecnico di Milano Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica ed Informazione - Politecnico di Milano ITALY","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipartimento di Elettronica ed Informazione - Politecnico di Milano Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114780313","display_name":"Andrea Marches","orcid":null},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Marches","raw_affiliation_strings":["Dipartimento di Elettronica ed Informazione - Politecnico di Milano ITALY","Dipartimento di Elettronica ed Informazione - Politecnico di Milano Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica ed Informazione - Politecnico di Milano ITALY","institution_ids":["https://openalex.org/I93860229"]},{"raw_affiliation_string":"Dipartimento di Elettronica ed Informazione - Politecnico di Milano Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12698834,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"40","issue":"10-12","first_page":"693","last_page":"696"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9118094444274902},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5833014249801636},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5826023817062378},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5383132100105286},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.5345937609672546},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46308571100234985},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.41820028424263},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.4180670976638794},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35840505361557007},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.23082119226455688},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17644530534744263},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.16997897624969482},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.13109278678894043},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12072506546974182}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9118094444274902},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5833014249801636},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5826023817062378},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5383132100105286},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.5345937609672546},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46308571100234985},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.41820028424263},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.4180670976638794},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35840505361557007},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.23082119226455688},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17644530534744263},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.16997897624969482},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.13109278678894043},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12072506546974182},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(94)90020-5","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)90020-5","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1969009567","https://openalex.org/W2110694148","https://openalex.org/W2168913743","https://openalex.org/W6676710709","https://openalex.org/W6684865458"],"related_works":["https://openalex.org/W59945861","https://openalex.org/W1551967076","https://openalex.org/W2151163382","https://openalex.org/W4256382613","https://openalex.org/W2117120814","https://openalex.org/W316163056","https://openalex.org/W2048159764","https://openalex.org/W2092972345","https://openalex.org/W2496740152","https://openalex.org/W1903431847"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}