{"id":"https://openalex.org/W2022515236","doi":"https://doi.org/10.1016/0165-6074(94)90016-7","title":"An explicitly declared delayed-branch mechanism for a superscalar architecture","display_name":"An explicitly declared delayed-branch mechanism for a superscalar architecture","publication_year":1994,"publication_date":"1994-12-01","ids":{"openalex":"https://openalex.org/W2022515236","doi":"https://doi.org/10.1016/0165-6074(94)90016-7","mag":"2022515236"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(94)90016-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)90016-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111377176","display_name":"Roger Collins","orcid":null},"institutions":[{"id":"https://openalex.org/I141584323","display_name":"University of Hertfordshire","ror":"https://ror.org/0267vjk41","country_code":"GB","type":"education","lineage":["https://openalex.org/I141584323"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Roger Collins","raw_affiliation_strings":["Department of Computer Science, University of Hertfordshire, College Lane, Hatfield, Herts. AL10 9AB, U.K"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Hertfordshire, College Lane, Hatfield, Herts. AL10 9AB, U.K","institution_ids":["https://openalex.org/I141584323"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103503628","display_name":"G.B. Steven","orcid":null},"institutions":[{"id":"https://openalex.org/I141584323","display_name":"University of Hertfordshire","ror":"https://ror.org/0267vjk41","country_code":"GB","type":"education","lineage":["https://openalex.org/I141584323"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Gordon Steven","raw_affiliation_strings":["Department of Computer Science, University of Hertfordshire, College Lane, Hatfield, Herts. AL10 9AB, U.K"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Hertfordshire, College Lane, Hatfield, Herts. AL10 9AB, U.K","institution_ids":["https://openalex.org/I141584323"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103503628","https://openalex.org/A5111377176"],"corresponding_institution_ids":["https://openalex.org/I141584323"],"apc_list":null,"apc_paid":null,"fwci":0.3831,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.65473349,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"40","issue":"10-12","first_page":"677","last_page":"680"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9147706031799316},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8042038679122925},{"id":"https://openalex.org/keywords/superscalar","display_name":"Superscalar","score":0.7678036093711853},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.7039580345153809},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6742237210273743},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.6226081252098083},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.6096718907356262},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5703651905059814},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.544448971748352},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.5080023407936096},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5044711828231812},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.4868732988834381},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.47052016854286194},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.45845097303390503},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4315170645713806},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.42576518654823303},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.4151137173175812},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4143097698688507},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3404504954814911},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.30656516551971436},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.26549607515335083},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.2478387951850891},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22770705819129944},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15223124623298645},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.13954445719718933}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9147706031799316},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8042038679122925},{"id":"https://openalex.org/C147101560","wikidata":"https://www.wikidata.org/wiki/Q1045706","display_name":"Superscalar","level":2,"score":0.7678036093711853},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.7039580345153809},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6742237210273743},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.6226081252098083},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.6096718907356262},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5703651905059814},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.544448971748352},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.5080023407936096},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5044711828231812},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.4868732988834381},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.47052016854286194},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.45845097303390503},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4315170645713806},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.42576518654823303},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.4151137173175812},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4143097698688507},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3404504954814911},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.30656516551971436},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.26549607515335083},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.2478387951850891},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22770705819129944},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15223124623298645},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.13954445719718933},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0165-6074(94)90016-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)90016-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},{"id":"pmh:oai:uhra.herts.ac.uk:2299/4876","is_oa":false,"landing_page_url":"http://hdl.handle.net/2299/4876","pdf_url":null,"source":{"id":"https://openalex.org/S4306400241","display_name":"University of Hertfordshire Research Archive (University of Hertfordshire)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I141584323","host_organization_name":"University of Hertfordshire","host_organization_lineage":["https://openalex.org/I141584323"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W641492617","https://openalex.org/W2143894108","https://openalex.org/W6681839573"],"related_works":["https://openalex.org/W25845550","https://openalex.org/W1552354207","https://openalex.org/W2533681803","https://openalex.org/W1538969934","https://openalex.org/W2150776253","https://openalex.org/W2411509464","https://openalex.org/W1499323045","https://openalex.org/W2142994974","https://openalex.org/W2022515236","https://openalex.org/W4249996369"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}