{"id":"https://openalex.org/W1995959888","doi":"https://doi.org/10.1016/0165-6074(94)00090-w","title":"On the routing of signals in parallel processor meshes","display_name":"On the routing of signals in parallel processor meshes","publication_year":1995,"publication_date":"1995-05-01","ids":{"openalex":"https://openalex.org/W1995959888","doi":"https://doi.org/10.1016/0165-6074(94)00090-w","mag":"1995959888"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(94)00090-w","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)00090-w","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109040792","display_name":"Constantinos V. Papadopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I154757721","display_name":"University of Piraeus","ror":"https://ror.org/02qs84g94","country_code":"GR","type":"education","lineage":["https://openalex.org/I154757721"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Constantinos V. Papadopoulos","raw_affiliation_strings":["Department of Informatics, University of Piraeus, Piraeus, Greece","[Dept. of Informatics, University of Piraeus, Piraeus, Greece]"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, University of Piraeus, Piraeus, Greece","institution_ids":["https://openalex.org/I154757721"]},{"raw_affiliation_string":"[Dept. of Informatics, University of Piraeus, Piraeus, Greece]","institution_ids":["https://openalex.org/I154757721"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5109040792"],"corresponding_institution_ids":["https://openalex.org/I154757721"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16348914,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"41","issue":"2","first_page":"171","last_page":"189"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8867830038070679},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.6863080263137817},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.5444040298461914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5321354866027832},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.5254249572753906},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5247393250465393},{"id":"https://openalex.org/keywords/static-routing","display_name":"Static routing","score":0.5229969024658203},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.48378297686576843},{"id":"https://openalex.org/keywords/message-passing","display_name":"Message passing","score":0.4146013855934143},{"id":"https://openalex.org/keywords/routing-table","display_name":"Routing table","score":0.4139890670776367},{"id":"https://openalex.org/keywords/routing-protocol","display_name":"Routing protocol","score":0.3648991286754608}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8867830038070679},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.6863080263137817},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.5444040298461914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5321354866027832},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.5254249572753906},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5247393250465393},{"id":"https://openalex.org/C204948658","wikidata":"https://www.wikidata.org/wiki/Q1119410","display_name":"Static routing","level":4,"score":0.5229969024658203},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.48378297686576843},{"id":"https://openalex.org/C854659","wikidata":"https://www.wikidata.org/wiki/Q1859284","display_name":"Message passing","level":2,"score":0.4146013855934143},{"id":"https://openalex.org/C184896649","wikidata":"https://www.wikidata.org/wiki/Q290066","display_name":"Routing table","level":4,"score":0.4139890670776367},{"id":"https://openalex.org/C104954878","wikidata":"https://www.wikidata.org/wiki/Q1648707","display_name":"Routing protocol","level":3,"score":0.3648991286754608}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(94)00090-w","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(94)00090-w","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W121712824","https://openalex.org/W1968606388","https://openalex.org/W2027284877","https://openalex.org/W2138711634","https://openalex.org/W2140978582","https://openalex.org/W2148919667","https://openalex.org/W2154323564","https://openalex.org/W4237609041","https://openalex.org/W6657085675","https://openalex.org/W6680689732","https://openalex.org/W6681171089","https://openalex.org/W6681851856"],"related_works":["https://openalex.org/W2481444631","https://openalex.org/W2139584334","https://openalex.org/W2967687368","https://openalex.org/W2168517869","https://openalex.org/W2127873929","https://openalex.org/W2887152003","https://openalex.org/W4234214763","https://openalex.org/W2171842537","https://openalex.org/W4255030887","https://openalex.org/W2246127887"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}