{"id":"https://openalex.org/W2087991272","doi":"https://doi.org/10.1016/0165-6074(93)90099-7","title":"VLSI implementation of digit-serial arithmetic modules","display_name":"VLSI implementation of digit-serial arithmetic modules","publication_year":1993,"publication_date":"1993-12-01","ids":{"openalex":"https://openalex.org/W2087991272","doi":"https://doi.org/10.1016/0165-6074(93)90099-7","mag":"2087991272"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(93)90099-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(93)90099-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088545509","display_name":"L. Bisdounis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"L. Bisdounis","raw_affiliation_strings":["VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004733695","display_name":"D.E. Metafas","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"D.E. Metafas","raw_affiliation_strings":["VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112420077","display_name":"A.M. Maras","orcid":null},"institutions":[{"id":"https://openalex.org/I142617266","display_name":"University of Crete","ror":"https://ror.org/00dr28g20","country_code":"GR","type":"education","lineage":["https://openalex.org/I142617266"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"A.M. Maras","raw_affiliation_strings":["Department of Electronics & Computer Engineering, University of Crete, 73100 Chania, Crete, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electronics & Computer Engineering, University of Crete, 73100 Chania, Crete, Greece","institution_ids":["https://openalex.org/I142617266"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038676218","display_name":"C. Mavridis","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"C. Mavridis","raw_affiliation_strings":["VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece"],"affiliations":[{"raw_affiliation_string":"VLSI Design Laboratory, Department of Electrical Engineering, University of Patras, 26110 Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5088545509"],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.22960109,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"39","issue":"2-5","first_page":"251","last_page":"254"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9408000111579895,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.925000011920929,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8681429028511047},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.698338508605957},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5745101571083069},{"id":"https://openalex.org/keywords/numerical-digit","display_name":"Numerical digit","score":0.5478900074958801},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5155501365661621},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.5137556791305542},{"id":"https://openalex.org/keywords/arbitrary-precision-arithmetic","display_name":"Arbitrary-precision arithmetic","score":0.47332748770713806},{"id":"https://openalex.org/keywords/saturation-arithmetic","display_name":"Saturation arithmetic","score":0.43544501066207886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4179791510105133},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.224798321723938},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20363131165504456},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09134659171104431}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8681429028511047},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.698338508605957},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5745101571083069},{"id":"https://openalex.org/C94957134","wikidata":"https://www.wikidata.org/wiki/Q82990","display_name":"Numerical digit","level":2,"score":0.5478900074958801},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5155501365661621},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.5137556791305542},{"id":"https://openalex.org/C83581934","wikidata":"https://www.wikidata.org/wiki/Q527381","display_name":"Arbitrary-precision arithmetic","level":2,"score":0.47332748770713806},{"id":"https://openalex.org/C182775192","wikidata":"https://www.wikidata.org/wiki/Q913725","display_name":"Saturation arithmetic","level":3,"score":0.43544501066207886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4179791510105133},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.224798321723938},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20363131165504456},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09134659171104431}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(93)90099-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(93)90099-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1563585604","https://openalex.org/W1578458555","https://openalex.org/W1987510526","https://openalex.org/W1995015114","https://openalex.org/W2057841079","https://openalex.org/W2061774327","https://openalex.org/W2102712964","https://openalex.org/W6647174289","https://openalex.org/W6648826832","https://openalex.org/W6666295657"],"related_works":["https://openalex.org/W2073476805","https://openalex.org/W1559551218","https://openalex.org/W1885677000","https://openalex.org/W2116803521","https://openalex.org/W2037029451","https://openalex.org/W1965905913","https://openalex.org/W1656092346","https://openalex.org/W2159910647","https://openalex.org/W1983325766","https://openalex.org/W2569747052"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
