{"id":"https://openalex.org/W2095181398","doi":"https://doi.org/10.1016/0165-6074(91)90325-n","title":"Optimization and architectural evaluation of regular combinatoric structures","display_name":"Optimization and architectural evaluation of regular combinatoric structures","publication_year":1991,"publication_date":"1991-08-01","ids":{"openalex":"https://openalex.org/W2095181398","doi":"https://doi.org/10.1016/0165-6074(91)90325-n","mag":"2095181398"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(91)90325-n","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(91)90325-n","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005353475","display_name":"Veronika Eisele","orcid":null},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]},{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Veronika Eisele","raw_affiliation_strings":["Siemens AG, Otto-Hahn Ring 6, D-8000 Munich 83, Germany","Technical University of Munich, Institute of Electronic Design Automation, D-8000 Munich 2, Germany"],"affiliations":[{"raw_affiliation_string":"Siemens AG, Otto-Hahn Ring 6, D-8000 Munich 83, Germany","institution_ids":["https://openalex.org/I1325886976"]},{"raw_affiliation_string":"Technical University of Munich, Institute of Electronic Design Automation, D-8000 Munich 2, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034576088","display_name":"D. Schmitt\u2010Landsiedel","orcid":"https://orcid.org/0000-0002-4817-5139"},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Doris Schmitt-Landsiedel","raw_affiliation_strings":["Siemens AG, Otto-Hahn Ring 6, D-8000 Munich 83, Germany","Siemens AG, Otto\u2010Hahn\u2010Ring 6, D\u20108000 Munich 83, Germany"],"affiliations":[{"raw_affiliation_string":"Siemens AG, Otto-Hahn Ring 6, D-8000 Munich 83, Germany","institution_ids":["https://openalex.org/I1325886976"]},{"raw_affiliation_string":"Siemens AG, Otto\u2010Hahn\u2010Ring 6, D\u20108000 Munich 83, Germany","institution_ids":["https://openalex.org/I1325886976"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5005353475"],"corresponding_institution_ids":["https://openalex.org/I1325886976","https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.215814,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"32","issue":"1-5","first_page":"69","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8205276131629944},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7222974896430969},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.6671760082244873},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5284329056739807},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5199926495552063},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.42977339029312134},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4226759076118469},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3701833486557007},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34670352935791016},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34078848361968994},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3355753719806671},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.14728081226348877},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1451091170310974},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09735819697380066},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09336856007575989},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08608806133270264},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08607673645019531}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8205276131629944},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7222974896430969},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.6671760082244873},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5284329056739807},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5199926495552063},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.42977339029312134},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4226759076118469},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3701833486557007},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34670352935791016},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34078848361968994},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3355753719806671},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.14728081226348877},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1451091170310974},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09735819697380066},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09336856007575989},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08608806133270264},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08607673645019531},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(91)90325-n","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(91)90325-n","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1561610472","https://openalex.org/W1982490658","https://openalex.org/W1992651809","https://openalex.org/W2144982614","https://openalex.org/W2168525081","https://openalex.org/W6684609300"],"related_works":["https://openalex.org/W3152981811","https://openalex.org/W2909211499","https://openalex.org/W3119688974","https://openalex.org/W2060067973","https://openalex.org/W2946075430","https://openalex.org/W1967469573","https://openalex.org/W2912276428","https://openalex.org/W2762653771","https://openalex.org/W2049650033","https://openalex.org/W3080559572"],"abstract_inverted_index":null,"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}