{"id":"https://openalex.org/W2014685527","doi":"https://doi.org/10.1016/0165-6074(90)90196-g","title":"A new concept for chip architecture design \u2014 Interactive architecture compilation from system specification to register-transfer algorithms","display_name":"A new concept for chip architecture design \u2014 Interactive architecture compilation from system specification to register-transfer algorithms","publication_year":1990,"publication_date":"1990-03-01","ids":{"openalex":"https://openalex.org/W2014685527","doi":"https://doi.org/10.1016/0165-6074(90)90196-g","mag":"2014685527"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(90)90196-g","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(90)90196-g","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030282071","display_name":"Uwe Wienkop","orcid":null},"institutions":[{"id":"https://openalex.org/I1325886976","display_name":"Siemens (Germany)","ror":"https://ror.org/059mq0909","country_code":"DE","type":"company","lineage":["https://openalex.org/I1325886976"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Uwe Wienkop","raw_affiliation_strings":["Siemens AG, Corporate R&D Laboratories D-8000 M\u00fcnchen 83 FRG"],"affiliations":[{"raw_affiliation_string":"Siemens AG, Corporate R&D Laboratories D-8000 M\u00fcnchen 83 FRG","institution_ids":["https://openalex.org/I1325886976"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5030282071"],"corresponding_institution_ids":["https://openalex.org/I1325886976"],"apc_list":null,"apc_paid":null,"fwci":0.3291,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61849711,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":"1-5","first_page":"319","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9185647964477539},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.7054698467254639},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6041870713233948},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.556769073009491},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48888128995895386},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38824695348739624},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32623183727264404},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3256981670856476}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9185647964477539},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.7054698467254639},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6041870713233948},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.556769073009491},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48888128995895386},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38824695348739624},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32623183727264404},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3256981670856476},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(90)90196-g","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(90)90196-g","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1965939051","https://openalex.org/W2162579037"],"related_works":["https://openalex.org/W4312941541","https://openalex.org/W2361019053","https://openalex.org/W2071125430","https://openalex.org/W624979004","https://openalex.org/W4238987864","https://openalex.org/W4232669059","https://openalex.org/W2332992073","https://openalex.org/W2064119831","https://openalex.org/W1606827233","https://openalex.org/W1944227976"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
