{"id":"https://openalex.org/W2080372360","doi":"https://doi.org/10.1016/0165-6074(88)90400-0","title":"A VLSI \u2018rest\u2019 processing element with improved bus connections (an evaluation)","display_name":"A VLSI \u2018rest\u2019 processing element with improved bus connections (an evaluation)","publication_year":1988,"publication_date":"1988-12-01","ids":{"openalex":"https://openalex.org/W2080372360","doi":"https://doi.org/10.1016/0165-6074(88)90400-0","mag":"2080372360"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(88)90400-0","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90400-0","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068232148","display_name":"Giovanni Aloisio","orcid":"https://orcid.org/0000-0001-5902-6983"},"institutions":[{"id":"https://openalex.org/I5561750","display_name":"University of Bari Aldo Moro","ror":"https://ror.org/027ynra39","country_code":"IT","type":"education","lineage":["https://openalex.org/I5561750"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Aloisio","raw_affiliation_strings":["Dipartimento di Elettrotecnica ed Elettronica, Facolt\u00e1 di Ingegneria \u2014 Universit\u00e1 di Bari, Italy","Univ. di Bari, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettrotecnica ed Elettronica, Facolt\u00e1 di Ingegneria \u2014 Universit\u00e1 di Bari, Italy","institution_ids":["https://openalex.org/I5561750"]},{"raw_affiliation_string":"Univ. di Bari, Italy#TAB#","institution_ids":["https://openalex.org/I5561750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020752895","display_name":"Vincenzo Di Lecce","orcid":"https://orcid.org/0000-0002-4878-185X"},"institutions":[{"id":"https://openalex.org/I5561750","display_name":"University of Bari Aldo Moro","ror":"https://ror.org/027ynra39","country_code":"IT","type":"education","lineage":["https://openalex.org/I5561750"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"V. Di Lecce","raw_affiliation_strings":["Dipartimento di Elettrotecnica ed Elettronica, Facolt\u00e1 di Ingegneria \u2014 Universit\u00e1 di Bari, Italy","Univ. di Bari, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettrotecnica ed Elettronica, Facolt\u00e1 di Ingegneria \u2014 Universit\u00e1 di Bari, Italy","institution_ids":["https://openalex.org/I5561750"]},{"raw_affiliation_string":"Univ. di Bari, Italy#TAB#","institution_ids":["https://openalex.org/I5561750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5561750"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24492469,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"22","issue":"5","first_page":"315","last_page":"323"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.883136510848999},{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.7156640887260437},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.6289615035057068},{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.5718406438827515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5136017799377441},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4928746223449707},{"id":"https://openalex.org/keywords/rest","display_name":"Rest (music)","score":0.43220239877700806},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.42762964963912964},{"id":"https://openalex.org/keywords/transmission","display_name":"Transmission (telecommunications)","score":0.4226316809654236},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3602652847766876},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35184916853904724},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34398555755615234},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.08866968750953674}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.883136510848999},{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.7156640887260437},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.6289615035057068},{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.5718406438827515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5136017799377441},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4928746223449707},{"id":"https://openalex.org/C77265313","wikidata":"https://www.wikidata.org/wiki/Q879844","display_name":"Rest (music)","level":2,"score":0.43220239877700806},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.42762964963912964},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.4226316809654236},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3602652847766876},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35184916853904724},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34398555755615234},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.08866968750953674},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C164705383","wikidata":"https://www.wikidata.org/wiki/Q10379","display_name":"Cardiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(88)90400-0","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90400-0","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1509443229","https://openalex.org/W1666015432","https://openalex.org/W1999736981","https://openalex.org/W2955234901","https://openalex.org/W6630562399"],"related_works":["https://openalex.org/W1980986440","https://openalex.org/W3158884034","https://openalex.org/W2167983067","https://openalex.org/W4388314704","https://openalex.org/W1971361763","https://openalex.org/W2014030893","https://openalex.org/W2065177255","https://openalex.org/W80911919","https://openalex.org/W2125719717","https://openalex.org/W2095387177"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-21T06:12:48.119943","created_date":"2025-10-10T00:00:00"}