{"id":"https://openalex.org/W1981187963","doi":"https://doi.org/10.1016/0165-6074(88)90042-7","title":"Hierarchical physical design system for VLSI-/370 microprocessor","display_name":"Hierarchical physical design system for VLSI-/370 microprocessor","publication_year":1988,"publication_date":"1988-08-01","ids":{"openalex":"https://openalex.org/W1981187963","doi":"https://doi.org/10.1016/0165-6074(88)90042-7","mag":"1981187963"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(88)90042-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90042-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001550422","display_name":"Uwe Schulz","orcid":"https://orcid.org/0000-0003-0362-8103"},"institutions":[{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Uwe Schulz","raw_affiliation_strings":["VLSI Logic Chip Development IBM Laboratories Boeblingen, Schoenaicher Str. 220 7030 Boeblingen, Germany"],"affiliations":[{"raw_affiliation_string":"VLSI Logic Chip Development IBM Laboratories Boeblingen, Schoenaicher Str. 220 7030 Boeblingen, Germany","institution_ids":["https://openalex.org/I4210095996"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5001550422"],"corresponding_institution_ids":["https://openalex.org/I4210095996"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0951785,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"1-5","first_page":"131","last_page":"135"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9055057764053345},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.76786208152771},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7478695511817932},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5771183371543884},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3790286183357239},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3432179093360901},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34250348806381226}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9055057764053345},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.76786208152771},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7478695511817932},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5771183371543884},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3790286183357239},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3432179093360901},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34250348806381226}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(88)90042-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90042-7","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W39373273","https://openalex.org/W2098026815","https://openalex.org/W2390545901","https://openalex.org/W1617740971","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1607753725","https://openalex.org/W1979789826","https://openalex.org/W2357771869","https://openalex.org/W1986774039"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
