{"id":"https://openalex.org/W2069235189","doi":"https://doi.org/10.1016/0165-6074(88)90026-9","title":"Logic synthesis in the design of the VLSI-/370 microprocessor","display_name":"Logic synthesis in the design of the VLSI-/370 microprocessor","publication_year":1988,"publication_date":"1988-08-01","ids":{"openalex":"https://openalex.org/W2069235189","doi":"https://doi.org/10.1016/0165-6074(88)90026-9","mag":"2069235189"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(88)90026-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90026-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074209586","display_name":"B. Kick","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095996","display_name":"IBM (Germany)","ror":"https://ror.org/00pm7rm97","country_code":"DE","type":"company","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210095996"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Bernhard Kick","raw_affiliation_strings":["IBM Laboratories, Dept. 3294 Schoenaicher Str. 220 7030 Boeblingen, West Germany"],"affiliations":[{"raw_affiliation_string":"IBM Laboratories, Dept. 3294 Schoenaicher Str. 220 7030 Boeblingen, West Germany","institution_ids":["https://openalex.org/I4210095996"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5074209586"],"corresponding_institution_ids":["https://openalex.org/I4210095996"],"apc_list":null,"apc_paid":null,"fwci":2.4512,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.89000418,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"24","issue":"1-5","first_page":"43","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8431828022003174},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7640063762664795},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7602840662002563},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6144789457321167},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.5720955729484558},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5561519265174866},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5010933876037598},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3413839340209961},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24987566471099854},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14531612396240234},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08869519829750061}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8431828022003174},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7640063762664795},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7602840662002563},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6144789457321167},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.5720955729484558},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5561519265174866},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5010933876037598},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3413839340209961},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24987566471099854},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14531612396240234},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08869519829750061},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(88)90026-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(88)90026-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1981777143","https://openalex.org/W2033316392","https://openalex.org/W2035076177","https://openalex.org/W2042418647","https://openalex.org/W2052320660","https://openalex.org/W2065371192","https://openalex.org/W2163205571","https://openalex.org/W4250956016","https://openalex.org/W6645980651","https://openalex.org/W6663535957"],"related_works":["https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1979789826","https://openalex.org/W101478184","https://openalex.org/W1986774039","https://openalex.org/W2135482679","https://openalex.org/W2035070505","https://openalex.org/W4241206086","https://openalex.org/W1973862904","https://openalex.org/W2081132365"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}