{"id":"https://openalex.org/W2044652550","doi":"https://doi.org/10.1016/0165-6074(86)90052-9","title":"An algorithm for the synthesis of processor structures from behavioural specifications","display_name":"An algorithm for the synthesis of processor structures from behavioural specifications","publication_year":1986,"publication_date":"1986-12-01","ids":{"openalex":"https://openalex.org/W2044652550","doi":"https://doi.org/10.1016/0165-6074(86)90052-9","mag":"2044652550"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(86)90052-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90052-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088968038","display_name":"Peter Marwedel","orcid":"https://orcid.org/0000-0001-5923-9145"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Peter Marwedel","raw_affiliation_strings":["Institut f\u00fcr Informatik und Praktische Mathematik Olshausenstr. 40-60, D-2300 Kiel, W. Germany"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Informatik und Praktische Mathematik Olshausenstr. 40-60, D-2300 Kiel, W. Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5088968038"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.4176,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.83813515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":"1-5","first_page":"251","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9035215377807617},{"id":"https://openalex.org/keywords/pascal","display_name":"Pascal (unit)","score":0.6243552565574646},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5734950304031372},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5150282382965088},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.45436906814575195},{"id":"https://openalex.org/keywords/functional-decomposition","display_name":"Functional decomposition","score":0.4438610076904297},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40429794788360596},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3625541031360626},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21015462279319763},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.15725046396255493},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08278864622116089}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9035215377807617},{"id":"https://openalex.org/C75608658","wikidata":"https://www.wikidata.org/wiki/Q44395","display_name":"Pascal (unit)","level":2,"score":0.6243552565574646},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5734950304031372},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5150282382965088},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.45436906814575195},{"id":"https://openalex.org/C12145135","wikidata":"https://www.wikidata.org/wiki/Q5215396","display_name":"Functional decomposition","level":2,"score":0.4438610076904297},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40429794788360596},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3625541031360626},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21015462279319763},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.15725046396255493},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08278864622116089},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0165-6074(86)90052-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90052-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.232.3116","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.232.3116","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/1986-Euromicro.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1597386284","https://openalex.org/W1771462325","https://openalex.org/W1972005541","https://openalex.org/W1990199656","https://openalex.org/W2024598204","https://openalex.org/W2032644556","https://openalex.org/W2072230590","https://openalex.org/W2118229154","https://openalex.org/W2146343280","https://openalex.org/W2154949934","https://openalex.org/W2167163830","https://openalex.org/W2169440157","https://openalex.org/W2593302965","https://openalex.org/W4242997105","https://openalex.org/W4251024117","https://openalex.org/W6643310923","https://openalex.org/W6677773528","https://openalex.org/W6681773852","https://openalex.org/W6683192874","https://openalex.org/W6684825526"],"related_works":["https://openalex.org/W4323268213","https://openalex.org/W2101047079","https://openalex.org/W4242128654","https://openalex.org/W2152549830","https://openalex.org/W1993744883","https://openalex.org/W3197720232","https://openalex.org/W2388387398","https://openalex.org/W3203996584","https://openalex.org/W2082549546","https://openalex.org/W3022773140"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
