{"id":"https://openalex.org/W2028195750","doi":"https://doi.org/10.1016/0165-6074(86)90035-9","title":"Compiling an RT level hardware description language into layout of NMOS cells","display_name":"Compiling an RT level hardware description language into layout of NMOS cells","publication_year":1986,"publication_date":"1986-12-01","ids":{"openalex":"https://openalex.org/W2028195750","doi":"https://doi.org/10.1016/0165-6074(86)90035-9","mag":"2028195750"},"language":"en","primary_location":{"id":"doi:10.1016/0165-6074(86)90035-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90035-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007933406","display_name":"Zainalabedin Navabi","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Zainalabedin Navabi","raw_affiliation_strings":["Electrical Engineering Department Sharif University of Technology P.O. Box 11365-8639 11365 Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department Sharif University of Technology P.O. Box 11365-8639 11365 Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5097746400","display_name":"Kia Doroudi","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Kia Doroudi","raw_affiliation_strings":["Electrical Engineering Department Sharif University of Technology P.O. Box 11365-8639 11365 Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department Sharif University of Technology P.O. Box 11365-8639 11365 Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.1854374,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":"1-5","first_page":"123","last_page":"129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8935865163803101},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7868770360946655},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.531543493270874},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.5094371438026428},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37413573265075684},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14604869484901428},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.049573421478271484}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8935865163803101},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7868770360946655},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.531543493270874},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5094371438026428},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37413573265075684},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14604869484901428},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.049573421478271484},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0165-6074(86)90035-9","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0165-6074(86)90035-9","pdf_url":null,"source":{"id":"https://openalex.org/S92214702","display_name":"Microprocessing and Microprogramming","issn_l":"0165-6074","issn":["0165-6074","1878-7061"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessing and Microprogramming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W228487683","https://openalex.org/W798442372","https://openalex.org/W1574542534","https://openalex.org/W1666015432","https://openalex.org/W1967575124","https://openalex.org/W2021467863","https://openalex.org/W2025642196","https://openalex.org/W2087443123","https://openalex.org/W2090740436","https://openalex.org/W2118929952","https://openalex.org/W2170097409","https://openalex.org/W3147630388","https://openalex.org/W6622849369","https://openalex.org/W6630108585","https://openalex.org/W6655694106"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2217098757","https://openalex.org/W2796085262","https://openalex.org/W2263373136","https://openalex.org/W190245591","https://openalex.org/W1650778624","https://openalex.org/W2545385022","https://openalex.org/W2022549222","https://openalex.org/W2082944690"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
