{"id":"https://openalex.org/W2017217154","doi":"https://doi.org/10.1016/0164-1212(94)00069-y","title":"Performance analysis of distributed memory computers with parallel node architecture","display_name":"Performance analysis of distributed memory computers with parallel node architecture","publication_year":1995,"publication_date":"1995-05-01","ids":{"openalex":"https://openalex.org/W2017217154","doi":"https://doi.org/10.1016/0164-1212(94)00069-y","mag":"2017217154"},"language":"en","primary_location":{"id":"doi:10.1016/0164-1212(94)00069-y","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0164-1212(94)00069-y","pdf_url":null,"source":{"id":"https://openalex.org/S37879656","display_name":"Journal of Systems and Software","issn_l":"0164-1212","issn":["0164-1212","1873-1228"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems and Software","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084631519","display_name":"Giulio Iannello","orcid":"https://orcid.org/0000-0003-3864-5800"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Giulio Iannello","raw_affiliation_strings":["Department of Computer Science and Systems, University of Naples, Naples, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Systems, University of Naples, Naples, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088599156","display_name":"Antonino Mazzeo","orcid":"https://orcid.org/0000-0002-4404-7738"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Antonino Mazzeo","raw_affiliation_strings":["Prof. Giulio Iannello, Dipartimento di Informatica e Sistemistica, Universit\u00e0 di Napoli, Via Claudio 21, 1-80125 Napoli, Italy"],"affiliations":[{"raw_affiliation_string":"Prof. Giulio Iannello, Dipartimento di Informatica e Sistemistica, Universit\u00e0 di Napoli, Via Claudio 21, 1-80125 Napoli, Italy","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045567395","display_name":"Nicola Mazzocca","orcid":"https://orcid.org/0000-0002-0401-9687"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nicola Mazzocca","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5084631519"],"corresponding_institution_ids":["https://openalex.org/I71267560"],"apc_list":{"value":3560,"currency":"USD","value_usd":3560},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18086124,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"29","issue":"2","first_page":"107","last_page":"120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mimd","display_name":"MIMD","score":0.8856745958328247},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8405404090881348},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.6782674193382263},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6602880954742432},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.6308727860450745},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5283499360084534},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5265398621559143},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.510646402835846},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4826243817806244},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.45337527990341187},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38373804092407227},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3144998550415039},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.2931024730205536},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1658812165260315},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.07734847068786621}],"concepts":[{"id":"https://openalex.org/C21032095","wikidata":"https://www.wikidata.org/wiki/Q1149237","display_name":"MIMD","level":2,"score":0.8856745958328247},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8405404090881348},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.6782674193382263},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6602880954742432},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.6308727860450745},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5283499360084534},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5265398621559143},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.510646402835846},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4826243817806244},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.45337527990341187},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38373804092407227},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3144998550415039},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.2931024730205536},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1658812165260315},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.07734847068786621},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0164-1212(94)00069-y","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0164-1212(94)00069-y","pdf_url":null,"source":{"id":"https://openalex.org/S37879656","display_name":"Journal of Systems and Software","issn_l":"0164-1212","issn":["0164-1212","1873-1228"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems and Software","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1559533846","https://openalex.org/W1998040188","https://openalex.org/W2026806304","https://openalex.org/W2045834214","https://openalex.org/W2066446185","https://openalex.org/W2071649025"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W2353146130","https://openalex.org/W4245497162","https://openalex.org/W1985165680","https://openalex.org/W1990817968","https://openalex.org/W2150064838","https://openalex.org/W2784603783","https://openalex.org/W1507921119","https://openalex.org/W2088823210","https://openalex.org/W2995170196"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}