{"id":"https://openalex.org/W2041698967","doi":"https://doi.org/10.1016/0164-1212(86)90005-1","title":"Analysis of a modified model for synchronous multiprocessor systems","display_name":"Analysis of a modified model for synchronous multiprocessor systems","publication_year":1986,"publication_date":"1986-11-01","ids":{"openalex":"https://openalex.org/W2041698967","doi":"https://doi.org/10.1016/0164-1212(86)90005-1","mag":"2041698967"},"language":"en","primary_location":{"id":"doi:10.1016/0164-1212(86)90005-1","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0164-1212(86)90005-1","pdf_url":null,"source":{"id":"https://openalex.org/S37879656","display_name":"Journal of Systems and Software","issn_l":"0164-1212","issn":["0164-1212","1873-1228"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems and Software","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110415148","display_name":"A. Pombortsis","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"A. Pombortsis","raw_affiliation_strings":["Aristotle University of Thessaloniki Greece","Aristotle University of Thessaloniki , Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Aristotle University of Thessaloniki Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Aristotle University of Thessaloniki , Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109250666","display_name":"C. Halatsis","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"C. Halatsis","raw_affiliation_strings":["Aristotle University of Thessaloniki Greece","Aristotle University of Thessaloniki , Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Aristotle University of Thessaloniki Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Aristotle University of Thessaloniki , Greece","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5110415148"],"corresponding_institution_ids":["https://openalex.org/I21370196"],"apc_list":{"value":3350,"currency":"USD","value_usd":3350},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.21818829,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"4","first_page":"361","last_page":"365"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7937198281288147},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7359756827354431},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6623736619949341},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.6462563872337341},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5998386144638062},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.5831052660942078},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5138097405433655},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.46964141726493835},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.41321536898612976},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3776243031024933},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3196631073951721},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.27564486861228943},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22941803932189941},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2104959487915039},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07574468851089478}],"concepts":[{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7937198281288147},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7359756827354431},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6623736619949341},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.6462563872337341},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5998386144638062},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.5831052660942078},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5138097405433655},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.46964141726493835},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.41321536898612976},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3776243031024933},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3196631073951721},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.27564486861228943},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22941803932189941},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2104959487915039},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07574468851089478}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0164-1212(86)90005-1","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0164-1212(86)90005-1","pdf_url":null,"source":{"id":"https://openalex.org/S37879656","display_name":"Journal of Systems and Software","issn_l":"0164-1212","issn":["0164-1212","1873-1228"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Systems and Software","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1754182032","https://openalex.org/W1937002962","https://openalex.org/W1976833094","https://openalex.org/W2006081551","https://openalex.org/W2015913288","https://openalex.org/W2032669921","https://openalex.org/W2040753126","https://openalex.org/W2068476500","https://openalex.org/W2085319748","https://openalex.org/W2155934476","https://openalex.org/W6667836630","https://openalex.org/W6683017401"],"related_works":["https://openalex.org/W2026512611","https://openalex.org/W4245497162","https://openalex.org/W1985165680","https://openalex.org/W2353146130","https://openalex.org/W2339366892","https://openalex.org/W2150064838","https://openalex.org/W2353073543","https://openalex.org/W233533876","https://openalex.org/W2604972926","https://openalex.org/W1990817968"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-10-10T00:00:00"}
