{"id":"https://openalex.org/W1995452481","doi":"https://doi.org/10.1016/0141-9331(94)90090-6","title":"Multi-level logic synthesis based on decomposition","display_name":"Multi-level logic synthesis based on decomposition","publication_year":1994,"publication_date":"1994-10-01","ids":{"openalex":"https://openalex.org/W1995452481","doi":"https://doi.org/10.1016/0141-9331(94)90090-6","mag":"1995452481"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(94)90090-6","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(94)90090-6","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051919904","display_name":"Tadeusz \u0141uba","orcid":"https://orcid.org/0000-0002-4965-7842"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Tadeusz \u0141uba","raw_affiliation_strings":["Warsaw University of Technology, Institute of Telecommunications, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland","Warsaw University of Technology, Institute of Telecommunications, ul. Nowowiejska 15/19, 00\u2010665 Warsaw, Poland"],"affiliations":[{"raw_affiliation_string":"Warsaw University of Technology, Institute of Telecommunications, ul. Nowowiejska 15/19, 00-665 Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Warsaw University of Technology, Institute of Telecommunications, ul. Nowowiejska 15/19, 00\u2010665 Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5051919904"],"corresponding_institution_ids":["https://openalex.org/I108403487"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.4084,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.65527611,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"18","issue":"8","first_page":"429","last_page":"437"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8349021673202515},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.7554398775100708},{"id":"https://openalex.org/keywords/functional-decomposition","display_name":"Functional decomposition","score":0.7125236988067627},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.6862062215805054},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.6498475074768066},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5519251823425293},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5406716465950012},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.4846542477607727},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45437970757484436},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4533121883869171},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.44727593660354614},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4467848539352417},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.41838428378105164},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3607276380062103},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3499869108200073},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15780019760131836},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09420844912528992},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.07476314902305603}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8349021673202515},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.7554398775100708},{"id":"https://openalex.org/C12145135","wikidata":"https://www.wikidata.org/wiki/Q5215396","display_name":"Functional decomposition","level":2,"score":0.7125236988067627},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.6862062215805054},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.6498475074768066},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5519251823425293},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5406716465950012},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.4846542477607727},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45437970757484436},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4533121883869171},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.44727593660354614},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4467848539352417},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.41838428378105164},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3607276380062103},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3499869108200073},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15780019760131836},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09420844912528992},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.07476314902305603},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0141-9331(94)90090-6","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(94)90090-6","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1517096063","https://openalex.org/W1546297343","https://openalex.org/W2012170251","https://openalex.org/W2059677035","https://openalex.org/W2081742683","https://openalex.org/W2105761964","https://openalex.org/W2116181020","https://openalex.org/W2125631309","https://openalex.org/W2128525630","https://openalex.org/W2135534764","https://openalex.org/W2160445406","https://openalex.org/W2317462728","https://openalex.org/W2736892343","https://openalex.org/W6632634233","https://openalex.org/W6678778472","https://openalex.org/W6679223554","https://openalex.org/W6680240799","https://openalex.org/W6683713795"],"related_works":["https://openalex.org/W1570722643","https://openalex.org/W2096895821","https://openalex.org/W2140127333","https://openalex.org/W2138447154","https://openalex.org/W1552215787","https://openalex.org/W2069533828","https://openalex.org/W2168127886","https://openalex.org/W2159720186","https://openalex.org/W2098306334","https://openalex.org/W4240072200"],"abstract_inverted_index":null,"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
