{"id":"https://openalex.org/W1977111335","doi":"https://doi.org/10.1016/0141-9331(93)90073-g","title":"Reconfiguring the boundaries of a mesh-connected array of processors with run-time programmable logic","display_name":"Reconfiguring the boundaries of a mesh-connected array of processors with run-time programmable logic","publication_year":1993,"publication_date":"1993-01-01","ids":{"openalex":"https://openalex.org/W1977111335","doi":"https://doi.org/10.1016/0141-9331(93)90073-g","mag":"1977111335"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(93)90073-g","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(93)90073-g","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11380/1247299","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030948871","display_name":"Rita Cucchiara","orcid":"https://orcid.org/0000-0002-2239-283X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R Cucchiara","raw_affiliation_strings":["Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043773944","display_name":"Tullio Salmon Cinotti","orcid":"https://orcid.org/0000-0002-6877-5254"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"T Salmon Cinotti","raw_affiliation_strings":["Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003174745","display_name":"Giovanni Neri","orcid":"https://orcid.org/0000-0001-7642-0130"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G Neri","raw_affiliation_strings":["Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071605541","display_name":"G. Rustichelli","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G Rustichelli","raw_affiliation_strings":["Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica Informatica e Sistemistica, Universit\u00e0 di Bologna, Viale Risorgimento 2, 40136 Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5043773944"],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.3779,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64142283,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":"2","first_page":"67","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8748116493225098},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.7657512426376343},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.6785597801208496},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6494676470756531},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5335054397583008},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5025572776794434},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4696601629257202},{"id":"https://openalex.org/keywords/processor-array","display_name":"Processor array","score":0.45904889702796936},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.4571305811405182},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41252416372299194},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1516994833946228},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09634801745414734}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8748116493225098},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.7657512426376343},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6785597801208496},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6494676470756531},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5335054397583008},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5025572776794434},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4696601629257202},{"id":"https://openalex.org/C2776189500","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Processor array","level":2,"score":0.45904889702796936},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.4571305811405182},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41252416372299194},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1516994833946228},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09634801745414734},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0141-9331(93)90073-g","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(93)90073-g","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},{"id":"pmh:oai:iris.unimore.it:11380/1247299","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1247299","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:iris.unimore.it:11380/1247299","is_oa":true,"landing_page_url":"http://hdl.handle.net/11380/1247299","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1944752010","https://openalex.org/W2084997371","https://openalex.org/W2088524508","https://openalex.org/W2157211828","https://openalex.org/W2321832090","https://openalex.org/W4297204443","https://openalex.org/W6640588342"],"related_works":["https://openalex.org/W2136725475","https://openalex.org/W2060937344","https://openalex.org/W196565075","https://openalex.org/W2059745206","https://openalex.org/W2096870795","https://openalex.org/W2156571376","https://openalex.org/W2495828995","https://openalex.org/W2165326264","https://openalex.org/W2539069741","https://openalex.org/W2378240303"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-05-13T08:25:38.343686","created_date":"2016-06-24T00:00:00"}