{"id":"https://openalex.org/W2067329722","doi":"https://doi.org/10.1016/0141-9331(93)90005-r","title":"Testability guidelines for multichip modules","display_name":"Testability guidelines for multichip modules","publication_year":1993,"publication_date":"1993-06-01","ids":{"openalex":"https://openalex.org/W2067329722","doi":"https://doi.org/10.1016/0141-9331(93)90005-r","mag":"2067329722"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(93)90005-r","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(93)90005-r","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077815362","display_name":"Kenneth E. Posse","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kenneth E Posse","raw_affiliation_strings":["Hewlett Packard Company, Manufacturing Test Division, PO Box 301, Loveland, Colorado 80537, USA"],"affiliations":[{"raw_affiliation_string":"Hewlett Packard Company, Manufacturing Test Division, PO Box 301, Loveland, Colorado 80537, USA","institution_ids":["https://openalex.org/I1324840837"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5077815362"],"corresponding_institution_ids":["https://openalex.org/I1324840837"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.18416473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":"5","first_page":"281","last_page":"287"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8740168809890747},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7880434989929199},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.4098752737045288},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35983479022979736},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33727049827575684}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8740168809890747},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7880434989929199},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.4098752737045288},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35983479022979736},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33727049827575684},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0141-9331(93)90005-r","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(93)90005-r","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2028504835","https://openalex.org/W2056462674","https://openalex.org/W2102383741","https://openalex.org/W2106571261","https://openalex.org/W2107479796","https://openalex.org/W2109845441","https://openalex.org/W2112769603","https://openalex.org/W2115037154","https://openalex.org/W2125134910","https://openalex.org/W2481378139","https://openalex.org/W4285719527","https://openalex.org/W6605234255","https://openalex.org/W6675055258","https://openalex.org/W6675928130","https://openalex.org/W6676259946","https://openalex.org/W6676447166","https://openalex.org/W6677316864","https://openalex.org/W6678688437","https://openalex.org/W6721771700"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2393524141","https://openalex.org/W2365130684","https://openalex.org/W2370255574","https://openalex.org/W2106502108","https://openalex.org/W2783560053","https://openalex.org/W2169676947","https://openalex.org/W2098899017","https://openalex.org/W2381807899","https://openalex.org/W3037788266"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}