{"id":"https://openalex.org/W2032367199","doi":"https://doi.org/10.1016/0141-9331(92)90076-6","title":"Fault-tolerant LPT task scheduling in multiprocessor systems","display_name":"Fault-tolerant LPT task scheduling in multiprocessor systems","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W2032367199","doi":"https://doi.org/10.1016/0141-9331(92)90076-6","mag":"2032367199"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(92)90076-6","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90076-6","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059080368","display_name":"Alan A. Bertossi","orcid":null},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alan A Bertossi","raw_affiliation_strings":["Dipartimento di Informatica, Universit\u00e0 di Pisa, Corso Italia 40, 56100 Pisa, Italy","Dipartimento di Informatica, Universit\u00e0 di Pisa Corso Italia 40, 56100 Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Pisa, Corso Italia 40, 56100 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Pisa Corso Italia 40, 56100 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046905749","display_name":"Luigi V. Mancini","orcid":"https://orcid.org/0000-0003-4859-2191"},"institutions":[{"id":"https://openalex.org/I108290504","display_name":"University of Pisa","ror":"https://ror.org/03ad39j10","country_code":"IT","type":"education","lineage":["https://openalex.org/I108290504"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Luigi Mancini","raw_affiliation_strings":["Dipartimento di Informatica, Universit\u00e0 di Pisa, Corso Italia 40, 56100 Pisa, Italy","Dipartimento di Informatica, Universit\u00e0 di Pisa Corso Italia 40, 56100 Pisa, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Pisa, Corso Italia 40, 56100 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]},{"raw_affiliation_string":"Dipartimento di Informatica, Universit\u00e0 di Pisa Corso Italia 40, 56100 Pisa, Italy","institution_ids":["https://openalex.org/I108290504"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5046905749"],"corresponding_institution_ids":["https://openalex.org/I108290504"],"apc_list":{"value":2200,"currency":"USD","value_usd":2200},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.19851452,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":"2","first_page":"91","last_page":"99"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9191184639930725},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.8356051445007324},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7320891618728638},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6566376090049744},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5991613268852234},{"id":"https://openalex.org/keywords/multiprocessor-scheduling","display_name":"Multiprocessor scheduling","score":0.5868343114852905},{"id":"https://openalex.org/keywords/backup","display_name":"Backup","score":0.5491292476654053},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.47572043538093567},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3951353430747986},{"id":"https://openalex.org/keywords/fair-share-scheduling","display_name":"Fair-share scheduling","score":0.2430691123008728},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21893608570098877},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.19860535860061646},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.07502385973930359}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9191184639930725},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.8356051445007324},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7320891618728638},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6566376090049744},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5991613268852234},{"id":"https://openalex.org/C85924588","wikidata":"https://www.wikidata.org/wiki/Q107419135","display_name":"Multiprocessor scheduling","level":5,"score":0.5868343114852905},{"id":"https://openalex.org/C2780945871","wikidata":"https://www.wikidata.org/wiki/Q194274","display_name":"Backup","level":2,"score":0.5491292476654053},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.47572043538093567},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3951353430747986},{"id":"https://openalex.org/C31689143","wikidata":"https://www.wikidata.org/wiki/Q733809","display_name":"Fair-share scheduling","level":3,"score":0.2430691123008728},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21893608570098877},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.19860535860061646},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.07502385973930359},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0141-9331(92)90076-6","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90076-6","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},{"id":"pmh:oai:iris.unitn.it:11572/23863","is_oa":false,"landing_page_url":"http://hdl.handle.net/11572/23863","pdf_url":null,"source":{"id":"https://openalex.org/S4306401913","display_name":"Institutional Research Information System (Universit\u00e0 degli Studi di Trento)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I193223587","host_organization_name":"University of Trento","host_organization_lineage":["https://openalex.org/I193223587"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W8792653","https://openalex.org/W634463279","https://openalex.org/W1545155892","https://openalex.org/W1841932260","https://openalex.org/W1895819589","https://openalex.org/W1968054699","https://openalex.org/W1991708881","https://openalex.org/W2109739361","https://openalex.org/W2149833774","https://openalex.org/W6639851029","https://openalex.org/W6644884274"],"related_works":["https://openalex.org/W2283291034","https://openalex.org/W1998948241","https://openalex.org/W4244289241","https://openalex.org/W2186708011","https://openalex.org/W2364223843","https://openalex.org/W4239937204","https://openalex.org/W2189025524","https://openalex.org/W2101964286","https://openalex.org/W2155564881","https://openalex.org/W1984223094"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}