{"id":"https://openalex.org/W2087151492","doi":"https://doi.org/10.1016/0141-9331(92)90066-3","title":"Design and VLSI implementation of an access processor for a decoupled architecture","display_name":"Design and VLSI implementation of an access processor for a decoupled architecture","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W2087151492","doi":"https://doi.org/10.1016/0141-9331(92)90066-3","mag":"2087151492"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(92)90066-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90066-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033563424","display_name":"P.T. Hulina","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Paul T Hulina","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112803780","display_name":"Lizyamma Kurian","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lizyamma Kurian","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010151984","display_name":"Eugene John","orcid":"https://orcid.org/0000-0001-9494-4894"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eugene B John","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038675075","display_name":"L.D. Coraor","orcid":null},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lee D Coraor","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, The Pennsylvania State University, University Park, PA 16802, USA","institution_ids":["https://openalex.org/I130769515"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5033563424"],"corresponding_institution_ids":["https://openalex.org/I130769515"],"apc_list":{"value":2290,"currency":"USD","value_usd":2290},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1920219,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":"5","first_page":"237","last_page":"247"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.915450930595398},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6900901794433594},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.5047632455825806},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.48708510398864746},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4746970534324646},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.46316444873809814},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.45413148403167725},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45347243547439575},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.4295833706855774},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.42503857612609863},{"id":"https://openalex.org/keywords/network-processor","display_name":"Network processor","score":0.4166327714920044},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39590713381767273},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.2761894464492798},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08405283093452454}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.915450930595398},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6900901794433594},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.5047632455825806},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.48708510398864746},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4746970534324646},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.46316444873809814},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.45413148403167725},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45347243547439575},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.4295833706855774},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.42503857612609863},{"id":"https://openalex.org/C74366991","wikidata":"https://www.wikidata.org/wiki/Q2755335","display_name":"Network processor","level":3,"score":0.4166327714920044},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39590713381767273},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.2761894464492798},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08405283093452454},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1016/0141-9331(92)90066-3","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90066-3","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.48.8420","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.8420","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.utexas.edu/projects/ece/lca/ps/micro92.ps","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332162","display_name":"Centers for Disease Control and Prevention","ror":"https://ror.org/042twtr12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W141175085","https://openalex.org/W165475780","https://openalex.org/W189565399","https://openalex.org/W1590954054","https://openalex.org/W1969648707","https://openalex.org/W1972077664","https://openalex.org/W1991984646","https://openalex.org/W1993715670","https://openalex.org/W1999339108","https://openalex.org/W2040721264","https://openalex.org/W2097997317","https://openalex.org/W2152479255","https://openalex.org/W2162858914","https://openalex.org/W4214669969","https://openalex.org/W4230201611","https://openalex.org/W4300992318","https://openalex.org/W6605773724","https://openalex.org/W6606732039","https://openalex.org/W6607747358","https://openalex.org/W6674895110"],"related_works":["https://openalex.org/W4250432526","https://openalex.org/W2101536355","https://openalex.org/W2562747857","https://openalex.org/W2133675875","https://openalex.org/W2883183116","https://openalex.org/W3081116756","https://openalex.org/W4252240422","https://openalex.org/W1722139759","https://openalex.org/W2127918040","https://openalex.org/W2556885209"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}