{"id":"https://openalex.org/W2091585132","doi":"https://doi.org/10.1016/0141-9331(92)90002-b","title":"Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study","display_name":"Scaling shared-bus multiprocessors with multiple buses and shared caches: a performance study","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W2091585132","doi":"https://doi.org/10.1016/0141-9331(92)90002-b","mag":"2091585132"},"language":"en","primary_location":{"id":"doi:10.1016/0141-9331(92)90002-b","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90002-b","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078540970","display_name":"Jonathan Bertoni","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Bertoni","raw_affiliation_strings":["Department of Computer Science and Engineering, University of Washington, USA","Dept. of Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]},{"raw_affiliation_string":"Dept. of Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111448746","display_name":"Jean-Loup Baer","orcid":null},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jean-Loup Baer","raw_affiliation_strings":["Department of Computer Science and Engineering, University of Washington, USA","Dept. of Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]},{"raw_affiliation_string":"Dept. of Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007627851","display_name":"Wen-Hann Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Hann Wang","raw_affiliation_strings":["Architecture Development Laboratory, Intel Corporation, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Architecture Development Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2290,"currency":"USD","value_usd":2290},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.19497365,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"16","issue":"7","first_page":"339","last_page":"350"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10974","display_name":"Advanced Queuing Theory Analysis","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1404","display_name":"Management Information Systems"},"field":{"id":"https://openalex.org/fields/14","display_name":"Business, Management and Accounting"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9125648736953735},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6325570344924927},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5516737699508667},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5495452284812927},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5191277861595154},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.47753965854644775},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4672194719314575},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4349595308303833},{"id":"https://openalex.org/keywords/false-sharing","display_name":"False sharing","score":0.4289831221103668},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4153098464012146},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41168636083602905},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3503352105617523},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3091663122177124},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25647246837615967},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16664981842041016},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.11923035979270935},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08541956543922424}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9125648736953735},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6325570344924927},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5516737699508667},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5495452284812927},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5191277861595154},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.47753965854644775},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4672194719314575},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4349595308303833},{"id":"https://openalex.org/C5165142","wikidata":"https://www.wikidata.org/wiki/Q5432732","display_name":"False sharing","level":5,"score":0.4289831221103668},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4153098464012146},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41168636083602905},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3503352105617523},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3091663122177124},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25647246837615967},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16664981842041016},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.11923035979270935},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08541956543922424}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/0141-9331(92)90002-b","is_oa":false,"landing_page_url":"https://doi.org/10.1016/0141-9331(92)90002-b","pdf_url":null,"source":{"id":"https://openalex.org/S195663827","display_name":"Microprocessors and Microsystems","issn_l":"0141-9331","issn":["0141-9331","1872-9436"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Microprocessors and Microsystems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W189999333","https://openalex.org/W1487783453","https://openalex.org/W1536557058","https://openalex.org/W1849557916","https://openalex.org/W1927092595","https://openalex.org/W1937002962","https://openalex.org/W1983707525","https://openalex.org/W1987381776","https://openalex.org/W2024682393","https://openalex.org/W2042921956","https://openalex.org/W2046097853","https://openalex.org/W2102730218","https://openalex.org/W2147638342","https://openalex.org/W2157340037","https://openalex.org/W2165352379","https://openalex.org/W2241145851","https://openalex.org/W6607747964","https://openalex.org/W6629156655","https://openalex.org/W6646342996","https://openalex.org/W6675720492","https://openalex.org/W6682041529","https://openalex.org/W6684408748","https://openalex.org/W6690420598","https://openalex.org/W6769495488","https://openalex.org/W6817935147"],"related_works":["https://openalex.org/W2145592252","https://openalex.org/W2050424343","https://openalex.org/W4255008187","https://openalex.org/W2407815036","https://openalex.org/W4250205214","https://openalex.org/W2036306661","https://openalex.org/W2143087414","https://openalex.org/W1797968800","https://openalex.org/W3216777841","https://openalex.org/W316086898"],"abstract_inverted_index":null,"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
