{"id":"https://openalex.org/W1977881339","doi":"https://doi.org/10.1007/s11227-006-0013-4","title":"Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform","display_name":"Computing all-pairs shortest paths on a linear systolic array and hardware realization on a reprogrammable FPGA platform","publication_year":2007,"publication_date":"2007-03-08","ids":{"openalex":"https://openalex.org/W1977881339","doi":"https://doi.org/10.1007/s11227-006-0013-4","mag":"1977881339"},"language":"en","primary_location":{"id":"doi:10.1007/s11227-006-0013-4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-006-0013-4","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103976030","display_name":"E.I. Milovanovi\u0107","orcid":"https://orcid.org/0000-0002-1905-4813"},"institutions":[{"id":"https://openalex.org/I152518017","display_name":"University of Nis","ror":"https://ror.org/00965bg92","country_code":"RS","type":"education","lineage":["https://openalex.org/I152518017"]}],"countries":["RS"],"is_corresponding":false,"raw_author_name":"E. I. Milovanovi\u0107","raw_affiliation_strings":["Faculty of Electronic Engineering, Beogradska 14, 18000, Ni\u0161, Serbia","Faculty of Electronic Engineering, Nis, Serbia 18000#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electronic Engineering, Beogradska 14, 18000, Ni\u0161, Serbia","institution_ids":["https://openalex.org/I152518017"]},{"raw_affiliation_string":"Faculty of Electronic Engineering, Nis, Serbia 18000#TAB#","institution_ids":["https://openalex.org/I152518017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083970126","display_name":"Igor Milovanovi\u0107","orcid":"https://orcid.org/0000-0003-2209-9606"},"institutions":[{"id":"https://openalex.org/I152518017","display_name":"University of Nis","ror":"https://ror.org/00965bg92","country_code":"RS","type":"education","lineage":["https://openalex.org/I152518017"]}],"countries":["RS"],"is_corresponding":false,"raw_author_name":"I. \u017d. Milovanovi\u0107","raw_affiliation_strings":["Faculty of Electronic Engineering, Beogradska 14, 18000, Ni\u0161, Serbia","Faculty of Electronic Engineering, Nis, Serbia 18000#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electronic Engineering, Beogradska 14, 18000, Ni\u0161, Serbia","institution_ids":["https://openalex.org/I152518017"]},{"raw_affiliation_string":"Faculty of Electronic Engineering, Nis, Serbia 18000#TAB#","institution_ids":["https://openalex.org/I152518017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078172547","display_name":"M. P. Bekakos","orcid":null},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"M. P. Bekakos","raw_affiliation_strings":["Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, 12, Vass, Sofias Str., Hellas, Greece","Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, 12, Vass, Sofias Str., Hellas, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015252134","display_name":"I. N. Tselepis","orcid":null},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"I. N. Tselepis","raw_affiliation_strings":["Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, 12, Vass, Sofias Str., Hellas, Greece","Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, 12, Vass, Sofias Str., Hellas, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, School of Engineering, Democritus University of Thrace, Hellas, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5015252134"],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":{"value":2390,"currency":"EUR","value_usd":2990},"apc_paid":null,"fwci":0.6293,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.69849148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"40","issue":"1","first_page":"49","last_page":"66"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8628853559494019},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.8193726539611816},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.7918422818183899},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7807278037071228},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.457528680562973},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4125359356403351},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32900506258010864},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3201133608818054},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2810661196708679},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.05930110812187195},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.05138465762138367}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8628853559494019},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.8193726539611816},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.7918422818183899},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7807278037071228},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.457528680562973},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4125359356403351},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32900506258010864},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3201133608818054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2810661196708679},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.05930110812187195},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.05138465762138367},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s11227-006-0013-4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-006-0013-4","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W38735320","https://openalex.org/W154945649","https://openalex.org/W1566364654","https://openalex.org/W1655990431","https://openalex.org/W1976515269","https://openalex.org/W1984087192","https://openalex.org/W2007572995","https://openalex.org/W2017967707","https://openalex.org/W2021848155","https://openalex.org/W2022822766","https://openalex.org/W2035659390","https://openalex.org/W2081578734","https://openalex.org/W2097113148","https://openalex.org/W2097755092","https://openalex.org/W2104734478","https://openalex.org/W2116144668","https://openalex.org/W2149899545","https://openalex.org/W2158901487","https://openalex.org/W2171603032","https://openalex.org/W2345331109","https://openalex.org/W2995746888","https://openalex.org/W4229992011","https://openalex.org/W4254861230","https://openalex.org/W4308562043"],"related_works":["https://openalex.org/W4240320454","https://openalex.org/W2070314832","https://openalex.org/W2022544890","https://openalex.org/W2394097730","https://openalex.org/W2347854075","https://openalex.org/W1967938402","https://openalex.org/W2050071657","https://openalex.org/W2132614232","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":null,"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-19T15:47:20.252518","created_date":"2025-10-10T00:00:00"}