{"id":"https://openalex.org/W1586753310","doi":"https://doi.org/10.1007/978-3-540-39864-6_25","title":"L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy","display_name":"L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W1586753310","doi":"https://doi.org/10.1007/978-3-540-39864-6_25","mag":"1586753310"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-39864-6_25","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39864-6_25","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008809486","display_name":"Philip Machanick","orcid":"https://orcid.org/0000-0001-6648-7032"},"institutions":[{"id":"https://openalex.org/I165143802","display_name":"University of Queensland","ror":"https://ror.org/00rqy9422","country_code":"AU","type":"education","lineage":["https://openalex.org/I165143802"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"Philip Machanick","raw_affiliation_strings":["School of ITEE, University of Queensland, Qld 4072, Brisbane, Australia"],"affiliations":[{"raw_affiliation_string":"School of ITEE, University of Queensland, Qld 4072, Brisbane, Australia","institution_ids":["https://openalex.org/I165143802"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015747882","display_name":"Zunaid Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I192619145","display_name":"University of the Witwatersrand","ror":"https://ror.org/03rp50x72","country_code":"ZA","type":"education","lineage":["https://openalex.org/I192619145"]}],"countries":["ZA"],"is_corresponding":false,"raw_author_name":"Zunaid Patel","raw_affiliation_strings":["School of Computer Science, University of the Witwatersrand, Private Bag 3, Johannesburg, 2050 Wits, South Africa"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, University of the Witwatersrand, Private Bag 3, Johannesburg, 2050 Wits, South Africa","institution_ids":["https://openalex.org/I192619145"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5008809486"],"corresponding_institution_ids":["https://openalex.org/I165143802"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.1837,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.75837563,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"305","last_page":"319"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/translation-lookaside-buffer","display_name":"Translation lookaside buffer","score":0.9288984537124634},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7888020277023315},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.7411415576934814},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7375918030738831},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6914149522781372},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6354115605354309},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.569174587726593},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5515015125274658},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5037512183189392},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4968765079975128},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4577431380748749},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4230839014053345},{"id":"https://openalex.org/keywords/page","display_name":"Page","score":0.4183056354522705},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3866865634918213},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3340255320072174},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.2755129933357239},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2744675874710083},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23322471976280212},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18650099635124207},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.12156590819358826},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.09179016947746277},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.061454325914382935}],"concepts":[{"id":"https://openalex.org/C116007543","wikidata":"https://www.wikidata.org/wiki/Q1071403","display_name":"Translation lookaside buffer","level":4,"score":0.9288984537124634},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7888020277023315},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.7411415576934814},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7375918030738831},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6914149522781372},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6354115605354309},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.569174587726593},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5515015125274658},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5037512183189392},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4968765079975128},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4577431380748749},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4230839014053345},{"id":"https://openalex.org/C33925742","wikidata":"https://www.wikidata.org/wiki/Q361698","display_name":"Page","level":2,"score":0.4183056354522705},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3866865634918213},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3340255320072174},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.2755129933357239},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2744675874710083},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23322471976280212},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18650099635124207},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.12156590819358826},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.09179016947746277},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.061454325914382935},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1007/978-3-540-39864-6_25","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39864-6_25","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.9.4570","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.9.4570","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.itee.uq.edu.au/~philip/Publications/_ACSAC/RAMpageTLB.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.93.7271","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.93.7271","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.itee.uq.edu.au/~philip/Publications/Techreports/2002/Reports/RAMpageTLBtechreport.pdf","raw_type":"text"},{"id":"pmh:oai:espace.library.uq.edu.au:UQ:10329","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306402388","display_name":"Queensland's institutional digital repository (The University of Queensland)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I165143802","host_organization_name":"The University of Queensland","host_organization_lineage":["https://openalex.org/I165143802"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1499849351","https://openalex.org/W1526636319","https://openalex.org/W1555915743","https://openalex.org/W1571201165","https://openalex.org/W1784627604","https://openalex.org/W1983096721","https://openalex.org/W1992969482","https://openalex.org/W1995140396","https://openalex.org/W2012960154","https://openalex.org/W2018761720","https://openalex.org/W2033508089","https://openalex.org/W2079778517","https://openalex.org/W2091919971","https://openalex.org/W2094390685","https://openalex.org/W2099958604","https://openalex.org/W2101366948","https://openalex.org/W2107354725","https://openalex.org/W2108117840","https://openalex.org/W2110815624","https://openalex.org/W2113785025","https://openalex.org/W2116578804","https://openalex.org/W2121050483","https://openalex.org/W2126818201","https://openalex.org/W2128125273","https://openalex.org/W2141342364","https://openalex.org/W2146634722","https://openalex.org/W2154346069","https://openalex.org/W2158493028","https://openalex.org/W2167181671","https://openalex.org/W2169395663","https://openalex.org/W2788962374","https://openalex.org/W2916411819","https://openalex.org/W3003597364","https://openalex.org/W4231652969","https://openalex.org/W4232714067","https://openalex.org/W4241252669","https://openalex.org/W4243440481","https://openalex.org/W4246870635","https://openalex.org/W4292169167"],"related_works":["https://openalex.org/W4234213705","https://openalex.org/W2152673879","https://openalex.org/W4252575112","https://openalex.org/W2555873975","https://openalex.org/W2362061522","https://openalex.org/W2152001105","https://openalex.org/W2170052546","https://openalex.org/W2119502203","https://openalex.org/W1586753310","https://openalex.org/W2093828978"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}