{"id":"https://openalex.org/W1592951471","doi":"https://doi.org/10.1007/3-540-46117-5_29","title":"High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices","display_name":"High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices","publication_year":2010,"publication_date":"2010-03-29","ids":{"openalex":"https://openalex.org/W1592951471","doi":"https://doi.org/10.1007/3-540-46117-5_29","mag":"1592951471"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-46117-5_29","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-46117-5_29","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032429005","display_name":"Rafa\u0142 Kie\u0142bik","orcid":"https://orcid.org/0000-0002-9695-1729"},"institutions":[{"id":"https://openalex.org/I188884621","display_name":"Lodz University of Technology","ror":"https://ror.org/00s8fpf52","country_code":"PL","type":"education","lineage":["https://openalex.org/I188884621"]},{"id":"https://openalex.org/I34250744","display_name":"University of \u0141\u00f3d\u017a","ror":"https://ror.org/05cq64r17","country_code":"PL","type":"education","lineage":["https://openalex.org/I34250744"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Rafal Kielbik","raw_affiliation_strings":["Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland","institution_ids":["https://openalex.org/I34250744","https://openalex.org/I188884621"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Juan Manuel Moreno","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Manuel Moreno","raw_affiliation_strings":["Department of Electronics Engineering, Technical University of Catalunya, c/ Gran Capita s/n, 08034, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Technical University of Catalunya, c/ Gran Capita s/n, 08034, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085564117","display_name":"Andrzej Napieralski","orcid":"https://orcid.org/0000-0002-3844-3435"},"institutions":[{"id":"https://openalex.org/I188884621","display_name":"Lodz University of Technology","ror":"https://ror.org/00s8fpf52","country_code":"PL","type":"education","lineage":["https://openalex.org/I188884621"]},{"id":"https://openalex.org/I34250744","display_name":"University of \u0141\u00f3d\u017a","ror":"https://ror.org/05cq64r17","country_code":"PL","type":"education","lineage":["https://openalex.org/I34250744"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Andrzej Napieralski","raw_affiliation_strings":["Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland","institution_ids":["https://openalex.org/I34250744","https://openalex.org/I188884621"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020471876","display_name":"Grzegorz Jab\u0142o\u0144ski","orcid":"https://orcid.org/0000-0003-0376-3583"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Grzegorz Jablonski","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5004068358","display_name":"Tomasz Szymanski","orcid":null},"institutions":[{"id":"https://openalex.org/I188884621","display_name":"Lodz University of Technology","ror":"https://ror.org/00s8fpf52","country_code":"PL","type":"education","lineage":["https://openalex.org/I188884621"]},{"id":"https://openalex.org/I34250744","display_name":"University of \u0141\u00f3d\u017a","ror":"https://ror.org/05cq64r17","country_code":"PL","type":"education","lineage":["https://openalex.org/I34250744"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tomasz Szymanski","raw_affiliation_strings":["Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronics and Computer Science, Technical University of Lodz, Al. Politechniki 11, 93-590, Lodz, Poland","institution_ids":["https://openalex.org/I34250744","https://openalex.org/I188884621"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5032429005"],"corresponding_institution_ids":["https://openalex.org/I188884621","https://openalex.org/I34250744"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.20187793,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"271","last_page":"280"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8303781151771545},{"id":"https://openalex.org/keywords/hypergraph","display_name":"Hypergraph","score":0.814603328704834},{"id":"https://openalex.org/keywords/vertex","display_name":"Vertex (graph theory)","score":0.6346156001091003},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.544213593006134},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.5134350061416626},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49767711758613586},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4073103964328766},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3926292657852173},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34358519315719604},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.2550532817840576},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.2254868745803833},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19519197940826416},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.12815001606941223},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10913941264152527}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8303781151771545},{"id":"https://openalex.org/C2781221856","wikidata":"https://www.wikidata.org/wiki/Q840247","display_name":"Hypergraph","level":2,"score":0.814603328704834},{"id":"https://openalex.org/C80899671","wikidata":"https://www.wikidata.org/wiki/Q1304193","display_name":"Vertex (graph theory)","level":3,"score":0.6346156001091003},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.544213593006134},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5134350061416626},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49767711758613586},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4073103964328766},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3926292657852173},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34358519315719604},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.2550532817840576},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2254868745803833},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19519197940826416},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.12815001606941223},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10913941264152527},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-46117-5_29","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-46117-5_29","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1594214086","https://openalex.org/W1830708738","https://openalex.org/W2095117703","https://openalex.org/W2100380502","https://openalex.org/W2126038221","https://openalex.org/W2139900512","https://openalex.org/W2145622053","https://openalex.org/W2155814884","https://openalex.org/W2162081665","https://openalex.org/W4236269389"],"related_works":["https://openalex.org/W4376608589","https://openalex.org/W3138003926","https://openalex.org/W4300037846","https://openalex.org/W1630514295","https://openalex.org/W1537073411","https://openalex.org/W2963081352","https://openalex.org/W4376608938","https://openalex.org/W4288275998","https://openalex.org/W2472555608","https://openalex.org/W4214498971"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-03-25T23:56:10.502304","created_date":"2025-10-10T00:00:00"}
