{"id":"https://openalex.org/W2071575532","doi":"https://doi.org/10.1007/s11590-006-0027-0","title":"An ILP based hierarchical global routing approach for VLSI ASIC design","display_name":"An ILP based hierarchical global routing approach for VLSI ASIC design","publication_year":2006,"publication_date":"2006-10-26","ids":{"openalex":"https://openalex.org/W2071575532","doi":"https://doi.org/10.1007/s11590-006-0027-0","mag":"2071575532"},"language":"en","primary_location":{"id":"doi:10.1007/s11590-006-0027-0","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11590-006-0027-0","pdf_url":null,"source":{"id":"https://openalex.org/S12647387","display_name":"Optimization Letters","issn_l":"1862-4472","issn":["1862-4472","1862-4480"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Optimization Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084415556","display_name":"Zhen Yang","orcid":"https://orcid.org/0000-0002-7728-916X"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Zhen Yang","raw_affiliation_strings":["Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada","(University of Waterloo)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"(University of Waterloo)","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036043351","display_name":"Anthony Vannelli","orcid":null},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Anthony Vannelli","raw_affiliation_strings":["Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada","(University of Waterloo)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, N2L 3G1, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"(University of Waterloo)","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011873620","display_name":"Shawki Areibi","orcid":"https://orcid.org/0000-0003-4832-0911"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Shawki Areibi","raw_affiliation_strings":["Engineering System and Computing, University of Guelph, Guelph, ON, N1G 2W1, Canada","University of Guelph\u2020"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Engineering System and Computing, University of Guelph, Guelph, ON, N1G 2W1, Canada","institution_ids":["https://openalex.org/I79817857"]},{"raw_affiliation_string":"University of Guelph\u2020","institution_ids":["https://openalex.org/I79817857"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2290,"currency":"EUR","value_usd":2890},"apc_paid":null,"fwci":3.8343,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.93073542,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"1","issue":"3","first_page":"281","last_page":"297"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7131761312484741},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6601783633232117},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6600322127342224},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.6484619975090027},{"id":"https://openalex.org/keywords/rounding","display_name":"Rounding","score":0.5497593283653259},{"id":"https://openalex.org/keywords/heuristic","display_name":"Heuristic","score":0.5472043752670288},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.49052566289901733},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42546606063842773},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4233846962451935},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.21175378561019897},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20849555730819702},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19110599160194397}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7131761312484741},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6601783633232117},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6600322127342224},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.6484619975090027},{"id":"https://openalex.org/C136625980","wikidata":"https://www.wikidata.org/wiki/Q663208","display_name":"Rounding","level":2,"score":0.5497593283653259},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5472043752670288},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.49052566289901733},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42546606063842773},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4233846962451935},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.21175378561019897},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20849555730819702},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19110599160194397},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/s11590-006-0027-0","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11590-006-0027-0","pdf_url":null,"source":{"id":"https://openalex.org/S12647387","display_name":"Optimization Letters","issn_l":"1862-4472","issn":["1862-4472","1862-4480"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Optimization Letters","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.126.9776","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.126.9776","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://orion.math.uwaterloo.ca/~hwolkowi/henry/reports/mitacs.d/pdf/Tony/pub6.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4399999976158142,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W62053619","https://openalex.org/W1522776502","https://openalex.org/W1987786682","https://openalex.org/W2030806798","https://openalex.org/W2071575532","https://openalex.org/W2124923188","https://openalex.org/W2135477945","https://openalex.org/W2158523263","https://openalex.org/W2159214117","https://openalex.org/W2159746935","https://openalex.org/W2168008340","https://openalex.org/W2178873339","https://openalex.org/W2409617698","https://openalex.org/W3142526730","https://openalex.org/W4205340856","https://openalex.org/W4302087205"],"related_works":["https://openalex.org/W2181385951","https://openalex.org/W2165367082","https://openalex.org/W4243934122","https://openalex.org/W1727049600","https://openalex.org/W2132668926","https://openalex.org/W2183812348","https://openalex.org/W2070693700","https://openalex.org/W1481897060","https://openalex.org/W3047211184","https://openalex.org/W3214737056"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
