{"id":"https://openalex.org/W3047943705","doi":"https://doi.org/10.1007/s11265-020-01545-y","title":"Enabling Dynamic System Integration on Maxeler HLS Platforms","display_name":"Enabling Dynamic System Integration on Maxeler HLS Platforms","publication_year":2020,"publication_date":"2020-08-09","ids":{"openalex":"https://openalex.org/W3047943705","doi":"https://doi.org/10.1007/s11265-020-01545-y","mag":"3047943705"},"language":"en","primary_location":{"id":"doi:10.1007/s11265-020-01545-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-020-01545-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-020-01545-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://link.springer.com/content/pdf/10.1007/s11265-020-01545-y.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060037681","display_name":"Charalampos Kritikakis","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Charalampos Kritikakis","raw_affiliation_strings":["The University of Manchester, Manchster, UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchster, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064000482","display_name":"Dirk Koch","orcid":"https://orcid.org/0000-0002-2568-4432"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Dirk Koch","raw_affiliation_strings":["The University of Manchester, Manchster, UK"],"affiliations":[{"raw_affiliation_string":"The University of Manchester, Manchster, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5060037681"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":{"value":2490,"currency":"EUR","value_usd":3090},"apc_paid":{"value":2490,"currency":"EUR","value_usd":3090},"fwci":0.2357,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48716864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"92","issue":"9","first_page":"887","last_page":"905"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.88709557056427},{"id":"https://openalex.org/keywords/stream-processing","display_name":"Stream processing","score":0.7783952951431274},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7774381637573242},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7438023686408997},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.729532778263092},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6733624339103699},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5978527665138245},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5289409756660461},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4972677528858185},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4761602580547333},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4582071304321289},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.44705408811569214},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4467426836490631},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.44087710976600647},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2683897912502289},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.17089304327964783},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1351265013217926}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.88709557056427},{"id":"https://openalex.org/C107027933","wikidata":"https://www.wikidata.org/wiki/Q2006448","display_name":"Stream processing","level":2,"score":0.7783952951431274},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7774381637573242},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7438023686408997},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.729532778263092},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6733624339103699},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5978527665138245},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5289409756660461},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4972677528858185},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4761602580547333},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4582071304321289},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.44705408811569214},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4467426836490631},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.44087710976600647},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2683897912502289},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.17089304327964783},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1351265013217926},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/s11265-020-01545-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-020-01545-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-020-01545-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire/60091d46-a467-4a0f-b543-aaa112151da4","is_oa":true,"landing_page_url":"https://research.manchester.ac.uk/en/publications/60091d46-a467-4a0f-b543-aaa112151da4","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Kritikakis, C & Koch, D 2020, 'Enabling Dynamic System Integration on Maxeler HLS Platforms', Journal of Signal Processing Systems, vol. 92, no. 9, pp. 887-905. https://doi.org/10.1007/s11265-020-01545-y","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.atira.dk:publications/60091d46-a467-4a0f-b543-aaa112151da4","is_oa":true,"landing_page_url":"http://link.springer.com/10.1007/s11265-020-01545-y","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Kritikakis, C & Koch, D 2020, 'Enabling Dynamic System Integration on Maxeler HLS Platforms', Journal of Signal Processing Systems, vol. 92, no. 9, pp. 887-905. https://doi.org/10.1007/s11265-020-01545-y","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"doi:10.1007/s11265-020-01545-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-020-01545-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-020-01545-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3047943705.pdf","grobid_xml":"https://content.openalex.org/works/W3047943705.grobid-xml"},"referenced_works_count":14,"referenced_works":["https://openalex.org/W92551552","https://openalex.org/W1966573088","https://openalex.org/W1984222112","https://openalex.org/W2095993144","https://openalex.org/W2118073772","https://openalex.org/W2122965263","https://openalex.org/W2164064042","https://openalex.org/W2183064252","https://openalex.org/W2232842728","https://openalex.org/W2557355796","https://openalex.org/W2612354329","https://openalex.org/W2786613774","https://openalex.org/W6689547164","https://openalex.org/W6737351731"],"related_works":["https://openalex.org/W1989140795","https://openalex.org/W2113327063","https://openalex.org/W1981433684","https://openalex.org/W2077180914","https://openalex.org/W2175563412","https://openalex.org/W2403307847","https://openalex.org/W2975331349","https://openalex.org/W3206653210","https://openalex.org/W2134941280","https://openalex.org/W2521218765"],"abstract_inverted_index":{"Abstract":[0],"High":[1],"Level":[2],"Synthesis":[3],"(HLS)":[4],"tools":[5],"enable":[6],"application":[7],"domain":[8],"experts":[9],"to":[10,80,113],"implement":[11,81],"applications":[12,22],"and":[13,35,54],"algorithms":[14],"on":[15],"FPGAs.":[16],"The":[17,118],"majority":[18],"of":[19,120,130],"present":[20],"FPGA":[21,84],"is":[23,30],"following":[24],"a":[25,49,82,95,106,127,131],"stream":[26,91],"processing":[27,92,135],"model":[28],"which":[29,110],"almost":[31],"entirely":[32],"implemented":[33],"statically":[34],"not":[36],"exploiting":[37],"the":[38,74,121],"benefits":[39,119],"enabled":[40],"by":[41,126],"partial":[42,56,103],"reconfiguration.":[43],"In":[44],"this":[45],"paper,":[46],"we":[47],"propose":[48],"generic":[50],"approach":[51],"for":[52,63],"implementing":[53],"using":[55],"reconfiguration":[57],"through":[58],"an":[59],"HLS":[60,69],"design":[61],"flow":[62,67,123],"Maxeler":[64,75],"platforms.":[65],"Our":[66],"extracts":[68],"generated":[70],"HDL":[71],"code":[72],"from":[73],"compilation":[76],"process":[77],"in":[78,105],"order":[79],"static":[83],"infrastructure":[85,99],"as":[86,88],"well":[87],"run-time":[89],"reconfigurable":[90,133],"modules.":[93],"As":[94],"distinct":[96],"feature,":[97],"our":[98],"can":[100],"accommodate":[101],"multiple":[102],"modules":[104],"pipeline":[107,136],"daisy-chained":[108],"manner,":[109],"aligns":[111],"directly":[112],"Maxeler\u2019s":[114],"dataflow":[115],"programming":[116],"paradigm.":[117],"proposed":[122],"are":[124],"demonstrated":[125],"case":[128],"study":[129],"dynamically":[132],"video":[134],"delivering":[137],"6.4GB/s":[138],"throughput.":[139]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-04-07T14:57:38.498316","created_date":"2025-10-10T00:00:00"}
