{"id":"https://openalex.org/W2799420360","doi":"https://doi.org/10.1007/s11265-018-1370-y","title":"SFF\u2014The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture","display_name":"SFF\u2014The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2799420360","doi":"https://doi.org/10.1007/s11265-018-1370-y","mag":"2799420360"},"language":"en","primary_location":{"id":"doi:10.1007/s11265-018-1370-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-018-1370-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-018-1370-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://link.springer.com/content/pdf/10.1007/s11265-018-1370-y.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082737603","display_name":"Carl Ingemarsson","orcid":"https://orcid.org/0000-0002-9902-8825"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"Carl Ingemarsson","raw_affiliation_strings":["Division of Computer Engineering, Department of Electrical Engineering, Link\u00f6ping University, SE\u2013581 83, Link\u00f6ping, Sweden"],"raw_orcid":"https://orcid.org/0000-0002-9902-8825","affiliations":[{"raw_affiliation_string":"Division of Computer Engineering, Department of Electrical Engineering, Link\u00f6ping University, SE\u2013581 83, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028423819","display_name":"Oscar Gustafsson","orcid":"https://orcid.org/0000-0003-3470-3911"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Oscar Gustafsson","raw_affiliation_strings":["Division of Computer Engineering, Department of Electrical Engineering, Link\u00f6ping University, SE\u2013581 83, Link\u00f6ping, Sweden"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Division of Computer Engineering, Department of Electrical Engineering, Link\u00f6ping University, SE\u2013581 83, Link\u00f6ping, Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082737603"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":{"value":2490,"currency":"EUR","value_usd":3090},"apc_paid":{"value":2490,"currency":"EUR","value_usd":3090},"fwci":1.1594,"has_fulltext":true,"cited_by_count":19,"citation_normalized_percentile":{"value":0.78898366,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"90","issue":"11","first_page":"1583","last_page":"1592"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9107682108879089},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8118141889572144},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7159343361854553},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7094065546989441},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.6848047971725464},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4488353133201599},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4393634796142578},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4210661053657532},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38511356711387634},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3372495770454407},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1642839014530182},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12088930606842041},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.05849289894104004}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9107682108879089},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8118141889572144},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7159343361854553},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7094065546989441},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.6848047971725464},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4488353133201599},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4393634796142578},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4210661053657532},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38511356711387634},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3372495770454407},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1642839014530182},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12088930606842041},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.05849289894104004},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/s11265-018-1370-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-018-1370-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-018-1370-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},{"id":"pmh:oai:DiVA.org:liu-150930","is_oa":true,"landing_page_url":"http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-150930","pdf_url":null,"source":{"id":"https://openalex.org/S4306401559","display_name":"KTH Publication Database DiVA (KTH Royal Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article in journal"}],"best_oa_location":{"id":"doi:10.1007/s11265-018-1370-y","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s11265-018-1370-y","pdf_url":"https://link.springer.com/content/pdf/10.1007/s11265-018-1370-y.pdf","source":{"id":"https://openalex.org/S11258463","display_name":"Journal of Signal Processing Systems","issn_l":"1939-8018","issn":["1939-8018","1939-8115"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Signal Processing Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5199999809265137,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2799420360.pdf","grobid_xml":"https://content.openalex.org/works/W2799420360.grobid-xml"},"referenced_works_count":26,"referenced_works":["https://openalex.org/W1900969659","https://openalex.org/W1923763959","https://openalex.org/W1983657887","https://openalex.org/W1987715275","https://openalex.org/W2015346536","https://openalex.org/W2029360173","https://openalex.org/W2029655296","https://openalex.org/W2035592458","https://openalex.org/W2042736563","https://openalex.org/W2049928955","https://openalex.org/W2054253789","https://openalex.org/W2055816427","https://openalex.org/W2056067847","https://openalex.org/W2065490696","https://openalex.org/W2096207106","https://openalex.org/W2099788829","https://openalex.org/W2104199626","https://openalex.org/W2110872491","https://openalex.org/W2119329660","https://openalex.org/W2132324656","https://openalex.org/W2161395307","https://openalex.org/W2317906089","https://openalex.org/W2394731906","https://openalex.org/W2516775472","https://openalex.org/W2724208071","https://openalex.org/W2896152796"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2129019972","https://openalex.org/W2038220260","https://openalex.org/W3164085601","https://openalex.org/W2126857316","https://openalex.org/W1522032972","https://openalex.org/W2113308450","https://openalex.org/W2139962137","https://openalex.org/W2340647897"],"abstract_inverted_index":{"In":[0],"this":[1,20,61],"paper,":[2],"a":[3,30],"fast":[4],"Fourier":[5],"transform":[6],"(FFT)":[7],"hardware":[8],"architecture":[9,46],"optimized":[10,69],"for":[11,35,78,88,103],"field-programmable":[12],"gate-arrays":[13],"(FPGAs)":[14],"is":[15,99],"proposed.":[16],"We":[17],"refer":[18],"to":[19],"as":[21,38],"the":[22,41,47,113,118,122],"single-stream":[23],"FPGA-optimized":[24],"feedforward":[25],"(SFF)":[26],"architecture.":[27],"By":[28],"using":[29],"stage":[31,62],"that":[32,73,112],"trades":[33],"adders":[34,74],"shift":[36,52,79,97],"registers":[37,53,80,98],"compared":[39],"with":[40,66],"single-path":[42],"delay":[43],"feedback":[44],"(SDF)":[45],"efficient":[48,93],"implementation":[49,94],"of":[50,95,121],"short":[51,96],"in":[54],"Xilinx":[55,107],"FPGAs":[56],"can":[57,63],"be":[58,64],"exploited.":[59],"Moreover,":[60],"combined":[65],"ordinary":[67],"or":[68],"SDF":[70],"stages":[71],"such":[72],"are":[75,86],"only":[76],"traded":[77],"when":[81,92],"beneficial.":[82],"The":[83,109],"resulting":[84],"structures":[85],"well-suited":[87],"FPGA":[89],"implementation,":[90],"especially":[91],"available.":[100],"This":[101],"holds":[102],"at":[104],"least":[105],"contemporary":[106],"FPGAs.":[108],"results":[110],"show":[111],"proposed":[114],"architectures":[115],"improve":[116],"on":[117],"current":[119],"state":[120],"art.":[123]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
