{"id":"https://openalex.org/W2048657616","doi":"https://doi.org/10.1007/s11227-011-0671-8","title":"Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files","display_name":"Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files","publication_year":2011,"publication_date":"2011-08-29","ids":{"openalex":"https://openalex.org/W2048657616","doi":"https://doi.org/10.1007/s11227-011-0671-8","mag":"2048657616"},"language":"en","primary_location":{"id":"doi:10.1007/s11227-011-0671-8","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-011-0671-8","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013513420","display_name":"Chung-Ju Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Chung-Ju Wu","raw_affiliation_strings":["Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","National Tsing Hua University"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"National Tsing Hua University","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051242077","display_name":"Yu\u2010Te Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Te Lin","raw_affiliation_strings":["Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","National Tsing Hua University"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"National Tsing Hua University","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109889402","display_name":"Jenq-Kuen Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jenq-Kuen Lee","raw_affiliation_strings":["Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","National Tsing Hua University"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, National Tsing-Hua University, Hsinchu, 30013, Taiwan","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"National Tsing Hua University","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5013513420"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":{"value":2390,"currency":"EUR","value_usd":2990},"apc_paid":null,"fwci":0.2588,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56199498,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"61","issue":"3","first_page":"1024","last_page":"1047"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.910486102104187},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.9073973894119263},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7085779905319214},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.7037419676780701},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.7034058570861816},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6167239546775818},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.580259382724762},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5185940265655518},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4603353440761566},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.44575902819633484},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.44251179695129395},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.4279133081436157},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3384805917739868},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20603981614112854},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19959518313407898},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.19509339332580566},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.15208914875984192},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.1412406861782074},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.08645427227020264}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.910486102104187},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9073973894119263},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7085779905319214},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.7037419676780701},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.7034058570861816},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6167239546775818},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.580259382724762},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5185940265655518},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4603353440761566},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.44575902819633484},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.44251179695129395},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.4279133081436157},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3384805917739868},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20603981614112854},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19959518313407898},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.19509339332580566},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.15208914875984192},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.1412406861782074},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.08645427227020264},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s11227-011-0671-8","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-011-0671-8","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W35475279","https://openalex.org/W105128281","https://openalex.org/W171206966","https://openalex.org/W1511141921","https://openalex.org/W1535111405","https://openalex.org/W1686420892","https://openalex.org/W1935371763","https://openalex.org/W1967889241","https://openalex.org/W1996162489","https://openalex.org/W2003804316","https://openalex.org/W2020636597","https://openalex.org/W2024060531","https://openalex.org/W2040167141","https://openalex.org/W2084451631","https://openalex.org/W2095798192","https://openalex.org/W2109220922","https://openalex.org/W2110937681","https://openalex.org/W2111348204","https://openalex.org/W2112324761","https://openalex.org/W2114030927","https://openalex.org/W2118866757","https://openalex.org/W2121624795","https://openalex.org/W2131929304","https://openalex.org/W2136636210","https://openalex.org/W2142682265","https://openalex.org/W2144271506","https://openalex.org/W2161455936","https://openalex.org/W2162987996","https://openalex.org/W2164775088","https://openalex.org/W2170886848","https://openalex.org/W2913035627","https://openalex.org/W3010524069","https://openalex.org/W3148529197","https://openalex.org/W4205342357","https://openalex.org/W4229975054","https://openalex.org/W4238014149","https://openalex.org/W4241926283","https://openalex.org/W4242172296","https://openalex.org/W4246493620"],"related_works":["https://openalex.org/W1942542608","https://openalex.org/W3022691489","https://openalex.org/W2353958330","https://openalex.org/W1967889241","https://openalex.org/W2165125411","https://openalex.org/W2581286023","https://openalex.org/W2911679140","https://openalex.org/W2000718530","https://openalex.org/W2162987996","https://openalex.org/W2054117411"],"abstract_inverted_index":null,"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}