{"id":"https://openalex.org/W2009349016","doi":"https://doi.org/10.1007/s11227-005-0287-y","title":"High-Visibility Debug-By-Design for FPGA Platforms","display_name":"High-Visibility Debug-By-Design for FPGA Platforms","publication_year":2005,"publication_date":"2005-03-04","ids":{"openalex":"https://openalex.org/W2009349016","doi":"https://doi.org/10.1007/s11227-005-0287-y","mag":"2009349016"},"language":"en","primary_location":{"id":"doi:10.1007/s11227-005-0287-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-005-0287-y","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039743217","display_name":"Peter Bellows","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Peter Bellows","raw_affiliation_strings":["USC Information Sciences Institute, USA","USC Information Sciences Institute USA"],"affiliations":[{"raw_affiliation_string":"USC Information Sciences Institute, USA","institution_ids":[]},{"raw_affiliation_string":"USC Information Sciences Institute USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5039743217"],"corresponding_institution_ids":[],"apc_list":{"value":2390,"currency":"EUR","value_usd":2990},"apc_paid":null,"fwci":0.7916,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74026777,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"32","issue":"2","first_page":"105","last_page":"118"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8748610019683838},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.874405026435852},{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.8428056240081787},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6687294244766235},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6089068055152893},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6061517596244812},{"id":"https://openalex.org/keywords/visibility","display_name":"Visibility","score":0.48470258712768555},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.46864575147628784},{"id":"https://openalex.org/keywords/background-debug-mode-interface","display_name":"Background debug mode interface","score":0.4546445310115814},{"id":"https://openalex.org/keywords/usability","display_name":"Usability","score":0.44988682866096497},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4322316646575928}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8748610019683838},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.874405026435852},{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.8428056240081787},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6687294244766235},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6089068055152893},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6061517596244812},{"id":"https://openalex.org/C123403432","wikidata":"https://www.wikidata.org/wiki/Q654068","display_name":"Visibility","level":2,"score":0.48470258712768555},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.46864575147628784},{"id":"https://openalex.org/C124774103","wikidata":"https://www.wikidata.org/wiki/Q4839640","display_name":"Background debug mode interface","level":3,"score":0.4546445310115814},{"id":"https://openalex.org/C170130773","wikidata":"https://www.wikidata.org/wiki/Q216378","display_name":"Usability","level":2,"score":0.44988682866096497},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4322316646575928},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/s11227-005-0287-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s11227-005-0287-y","pdf_url":null,"source":{"id":"https://openalex.org/S32326811","display_name":"The Journal of Supercomputing","issn_l":"0920-8542","issn":["0920-8542","1573-0484"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Journal of Supercomputing","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.130.7635","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.130.7635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://68.153.197.235/csrea/ers2021.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1541614440","https://openalex.org/W1595904496","https://openalex.org/W2056566747","https://openalex.org/W2086750897","https://openalex.org/W2105993342","https://openalex.org/W2115539652","https://openalex.org/W2140166005","https://openalex.org/W2152530860","https://openalex.org/W2156253418","https://openalex.org/W4241851591"],"related_works":["https://openalex.org/W4312911728","https://openalex.org/W2103423582","https://openalex.org/W2366346238","https://openalex.org/W2107662612","https://openalex.org/W4312993667","https://openalex.org/W2114320580","https://openalex.org/W2791836533","https://openalex.org/W4212932124","https://openalex.org/W1967048002","https://openalex.org/W2400831214"],"abstract_inverted_index":null,"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
