{"id":"https://openalex.org/W2555826082","doi":"https://doi.org/10.1007/s10766-016-0473-y","title":"DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool","display_name":"DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool","publication_year":2016,"publication_date":"2016-11-15","ids":{"openalex":"https://openalex.org/W2555826082","doi":"https://doi.org/10.1007/s10766-016-0473-y","mag":"2555826082"},"language":"en","primary_location":{"id":"doi:10.1007/s10766-016-0473-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10766-016-0473-y","pdf_url":null,"source":{"id":"https://openalex.org/S148521650","display_name":"International Journal of Parallel Programming","issn_l":"0885-7458","issn":["0885-7458","1573-7640"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Parallel Programming","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090870819","display_name":"Christian Weis","orcid":"https://orcid.org/0000-0002-4152-0200"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Christian Weis","raw_affiliation_strings":["Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013911109","display_name":"Abdul Mutaal","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Abdul Mutaal","raw_affiliation_strings":["Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054027510","display_name":"Omar Naji","orcid":null},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Omar Naji","raw_affiliation_strings":["Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010135168","display_name":"Matthias Jung","orcid":"https://orcid.org/0000-0003-0036-2143"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Matthias Jung","raw_affiliation_strings":["Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045491281","display_name":"Andreas Hansson","orcid":null},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andreas Hansson","raw_affiliation_strings":["Research, ARM Ltd., Cambridge, UK"],"affiliations":[{"raw_affiliation_string":"Research, ARM Ltd., Cambridge, UK","institution_ids":["https://openalex.org/I2801109035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059285190","display_name":"Norbert Wehn","orcid":"https://orcid.org/0000-0002-9010-086X"},"institutions":[{"id":"https://openalex.org/I153267046","display_name":"University of Kaiserslautern","ror":"https://ror.org/04zrf7b53","country_code":"DE","type":"education","lineage":["https://openalex.org/I153267046"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Norbert Wehn","raw_affiliation_strings":["Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Design Research Group, University of Kaiserslautern, Kaiserslautern, Germany","institution_ids":["https://openalex.org/I153267046"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5090870819"],"corresponding_institution_ids":["https://openalex.org/I153267046"],"apc_list":{"value":2290,"currency":"EUR","value_usd":2890},"apc_paid":null,"fwci":0.9651,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.75409083,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"45","issue":"6","first_page":"1566","last_page":"1591"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9069271087646484},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.7848420739173889},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7765904664993286},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7720662951469421},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.7623957395553589},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.582940936088562},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.41663485765457153},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29282671213150024},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.19560280442237854},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.10576316714286804},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.08696964383125305}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9069271087646484},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.7848420739173889},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7765904664993286},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7720662951469421},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.7623957395553589},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.582940936088562},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.41663485765457153},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29282671213150024},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.19560280442237854},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10576316714286804},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.08696964383125305},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s10766-016-0473-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10766-016-0473-y","pdf_url":null,"source":{"id":"https://openalex.org/S148521650","display_name":"International Journal of Parallel Programming","issn_l":"0885-7458","issn":["0885-7458","1573-7640"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Parallel Programming","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W42114374","https://openalex.org/W1969423394","https://openalex.org/W1980891674","https://openalex.org/W2017525960","https://openalex.org/W2034861439","https://openalex.org/W2038212693","https://openalex.org/W2039742886","https://openalex.org/W2040681711","https://openalex.org/W2058539177","https://openalex.org/W2095867783","https://openalex.org/W2100516830","https://openalex.org/W2147657366","https://openalex.org/W2150909864","https://openalex.org/W2161264993","https://openalex.org/W2162639668","https://openalex.org/W2164586147","https://openalex.org/W2272558892","https://openalex.org/W2288675187","https://openalex.org/W3103339143","https://openalex.org/W4243225647"],"related_works":["https://openalex.org/W4293430534","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2800412005","https://openalex.org/W2122646225","https://openalex.org/W3140615508","https://openalex.org/W4291214134","https://openalex.org/W2912837441","https://openalex.org/W2029945810","https://openalex.org/W1954780666"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
