{"id":"https://openalex.org/W2302439350","doi":"https://doi.org/10.1007/s10617-016-9174-4","title":"Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism","display_name":"Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism","publication_year":2016,"publication_date":"2016-03-17","ids":{"openalex":"https://openalex.org/W2302439350","doi":"https://doi.org/10.1007/s10617-016-9174-4","mag":"2302439350"},"language":"en","primary_location":{"id":"doi:10.1007/s10617-016-9174-4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10617-016-9174-4","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034556690","display_name":"Marcelo Brandalero","orcid":"https://orcid.org/0000-0002-0012-7023"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Marcelo Brandalero","raw_affiliation_strings":["Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul, Av. Bento Gon\u00e7alves, 9500, Porto Alegre, Brazil"],"raw_orcid":"https://orcid.org/0000-0002-0012-7023","affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul, Av. Bento Gon\u00e7alves, 9500, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078952423","display_name":"Antonio Carlos Schneider Beck","orcid":"https://orcid.org/0000-0002-4492-1747"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Antonio Carlos S. Beck","raw_affiliation_strings":["Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul, Av. Bento Gon\u00e7alves, 9500, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto de Inform\u00e1tica, Universidade Federal do Rio Grande do Sul, Av. Bento Gon\u00e7alves, 9500, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5034556690"],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":{"value":3190,"currency":"USD","value_usd":3190},"apc_paid":null,"fwci":0.4347,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68223972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"20","issue":"2","first_page":"155","last_page":"169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8877530097961426},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.7295986413955688},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.6069599390029907},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5847628712654114},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5809934139251709},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5399280786514282},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.5183869004249573},{"id":"https://openalex.org/keywords/fetch","display_name":"Fetch","score":0.4866393506526947},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.4642295241355896},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4631957411766052},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.45252174139022827},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.41558289527893066},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3994446396827698},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.35573405027389526},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21015051007270813},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.1814921796321869},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.11623996496200562},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.09320610761642456}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8877530097961426},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.7295986413955688},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.6069599390029907},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5847628712654114},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5809934139251709},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5399280786514282},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.5183869004249573},{"id":"https://openalex.org/C131918245","wikidata":"https://www.wikidata.org/wiki/Q1409090","display_name":"Fetch","level":2,"score":0.4866393506526947},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.4642295241355896},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4631957411766052},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.45252174139022827},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.41558289527893066},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3994446396827698},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.35573405027389526},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21015051007270813},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.1814921796321869},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.11623996496200562},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.09320610761642456},{"id":"https://openalex.org/C111368507","wikidata":"https://www.wikidata.org/wiki/Q43518","display_name":"Oceanography","level":1,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s10617-016-9174-4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10617-016-9174-4","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","score":0.47999998927116394,"display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W1492601037","https://openalex.org/W1555915743","https://openalex.org/W1563597203","https://openalex.org/W1686420892","https://openalex.org/W1975489482","https://openalex.org/W1991577384","https://openalex.org/W2013471886","https://openalex.org/W2022814163","https://openalex.org/W2038509324","https://openalex.org/W2043398903","https://openalex.org/W2043724035","https://openalex.org/W2088098451","https://openalex.org/W2103742924","https://openalex.org/W2115294662","https://openalex.org/W2129192659","https://openalex.org/W2153402554","https://openalex.org/W2156174665","https://openalex.org/W2165423885","https://openalex.org/W2293877842","https://openalex.org/W2490237269","https://openalex.org/W2544732887","https://openalex.org/W2611703827","https://openalex.org/W4232751114","https://openalex.org/W4236892585","https://openalex.org/W4242976792"],"related_works":["https://openalex.org/W2611818882","https://openalex.org/W2039534605","https://openalex.org/W2126395326","https://openalex.org/W2148099609","https://openalex.org/W1995794264","https://openalex.org/W2071053528","https://openalex.org/W4241382821","https://openalex.org/W2008972959","https://openalex.org/W2131190522","https://openalex.org/W2515308961"],"abstract_inverted_index":null,"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-23T08:03:31.855105","created_date":"2025-10-10T00:00:00"}
