{"id":"https://openalex.org/W1999283398","doi":"https://doi.org/10.1007/s10617-010-9051-5","title":"A scheduler synthesis methodology for joint SW/HW design exploration of SoC","display_name":"A scheduler synthesis methodology for joint SW/HW design exploration of SoC","publication_year":2010,"publication_date":"2010-03-15","ids":{"openalex":"https://openalex.org/W1999283398","doi":"https://doi.org/10.1007/s10617-010-9051-5","mag":"1999283398"},"language":"en","primary_location":{"id":"doi:10.1007/s10617-010-9051-5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10617-010-9051-5","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11336/16379","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025223211","display_name":"Ismail Assayad","orcid":"https://orcid.org/0000-0002-6939-6125"},"institutions":[{"id":"https://openalex.org/I99297268","display_name":"University of Hassan II Casablanca","ror":"https://ror.org/001q4kn48","country_code":"MA","type":"education","lineage":["https://openalex.org/I99297268"]}],"countries":["MA"],"is_corresponding":true,"raw_author_name":"Ismail Assayad","raw_affiliation_strings":["ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco","ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco#TAB#"],"affiliations":[{"raw_affiliation_string":"ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco","institution_ids":["https://openalex.org/I99297268"]},{"raw_affiliation_string":"ENSEM, University of Hassan II Ain Chock, Oasis Casablanca, Morocco#TAB#","institution_ids":["https://openalex.org/I99297268"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025693758","display_name":"Sergio Yovine","orcid":"https://orcid.org/0000-0002-2737-4382"},"institutions":[{"id":"https://openalex.org/I151201029","display_name":"Consejo Nacional de Investigaciones Cient\u00edficas y T\u00e9cnicas","ror":"https://ror.org/03cqe8w59","country_code":"AR","type":"funder","lineage":["https://openalex.org/I151201029","https://openalex.org/I4210123736","https://openalex.org/I4387155568"]},{"id":"https://openalex.org/I24354313","display_name":"University of Buenos Aires","ror":"https://ror.org/0081fs513","country_code":"AR","type":"education","lineage":["https://openalex.org/I24354313"]}],"countries":["AR"],"is_corresponding":false,"raw_author_name":"Sergio Yovine","raw_affiliation_strings":["Departamento de Computacion, Universidad de Buenos Aires, and Researcher at CONICET, Buenos Aires, Argentina","Departamento de Computacion, Universidad de Buenos Aires, and Researcher at CONICET, Buenos Aires, Argentina#TAB#"],"affiliations":[{"raw_affiliation_string":"Departamento de Computacion, Universidad de Buenos Aires, and Researcher at CONICET, Buenos Aires, Argentina","institution_ids":["https://openalex.org/I24354313","https://openalex.org/I151201029"]},{"raw_affiliation_string":"Departamento de Computacion, Universidad de Buenos Aires, and Researcher at CONICET, Buenos Aires, Argentina#TAB#","institution_ids":["https://openalex.org/I24354313"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025223211"],"corresponding_institution_ids":["https://openalex.org/I99297268"],"apc_list":{"value":2490,"currency":"EUR","value_usd":3190},"apc_paid":null,"fwci":1.2635,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80420426,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"14","issue":"2","first_page":"75","last_page":"103"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8542960286140442},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7979165315628052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6090939044952393},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.5403104424476624},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5394433736801147},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5208911895751953},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.4636382460594177},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4556347727775574},{"id":"https://openalex.org/keywords/embedded-software","display_name":"Embedded software","score":0.44670048356056213},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.42296451330184937},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23001202940940857},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1737988293170929}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8542960286140442},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7979165315628052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6090939044952393},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.5403104424476624},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5394433736801147},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5208911895751953},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4636382460594177},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4556347727775574},{"id":"https://openalex.org/C154488198","wikidata":"https://www.wikidata.org/wiki/Q1335007","display_name":"Embedded software","level":3,"score":0.44670048356056213},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.42296451330184937},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23001202940940857},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1737988293170929},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/s10617-010-9051-5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s10617-010-9051-5","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"},{"id":"pmh:oai:ri.conicet.gov.ar:11336/16379","is_oa":true,"landing_page_url":"http://hdl.handle.net/11336/16379","pdf_url":null,"source":{"id":"https://openalex.org/S4306401400","display_name":"Conicet","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210104196","host_organization_name":"Centro Cient\u00edfico Tecnol\u00f3gico - Nordeste","host_organization_lineage":["https://openalex.org/I4210104196"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-sa","license_id":"https://openalex.org/licenses/cc-by-nc-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:ri.conicet.gov.ar:11336/16379","is_oa":true,"landing_page_url":"http://hdl.handle.net/11336/16379","pdf_url":null,"source":{"id":"https://openalex.org/S4306401400","display_name":"Conicet","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210104196","host_organization_name":"Centro Cient\u00edfico Tecnol\u00f3gico - Nordeste","host_organization_lineage":["https://openalex.org/I4210104196"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-sa","license_id":"https://openalex.org/licenses/cc-by-nc-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W107611607","https://openalex.org/W138537086","https://openalex.org/W1481733864","https://openalex.org/W1489719656","https://openalex.org/W1494407119","https://openalex.org/W1501652040","https://openalex.org/W1522154164","https://openalex.org/W1575656359","https://openalex.org/W1848643860","https://openalex.org/W1990741304","https://openalex.org/W2051542972","https://openalex.org/W2061341864","https://openalex.org/W2116182251","https://openalex.org/W2128391427","https://openalex.org/W2128904268","https://openalex.org/W2130436940","https://openalex.org/W2135413054","https://openalex.org/W2135728859","https://openalex.org/W2140755459","https://openalex.org/W2149062727","https://openalex.org/W2150408604","https://openalex.org/W2156475585","https://openalex.org/W2163075631","https://openalex.org/W2167240608","https://openalex.org/W2167386883","https://openalex.org/W2405902569","https://openalex.org/W2613746377","https://openalex.org/W3151281160"],"related_works":["https://openalex.org/W2145092870","https://openalex.org/W3148775727","https://openalex.org/W2178653557","https://openalex.org/W2129678152","https://openalex.org/W2540211551","https://openalex.org/W3151908233","https://openalex.org/W2057268231","https://openalex.org/W1508156141","https://openalex.org/W2120080222","https://openalex.org/W2059569687"],"abstract_inverted_index":null,"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}