{"id":"https://openalex.org/W2106171663","doi":"https://doi.org/10.1007/s00450-011-0169-x","title":"Designing and dynamically load balancing hybrid LU for multi/many-core","display_name":"Designing and dynamically load balancing hybrid LU for multi/many-core","publication_year":2011,"publication_date":"2011-04-13","ids":{"openalex":"https://openalex.org/W2106171663","doi":"https://doi.org/10.1007/s00450-011-0169-x","mag":"2106171663"},"language":"en","primary_location":{"id":"doi:10.1007/s00450-011-0169-x","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00450-011-0169-x","pdf_url":null,"source":{"id":"https://openalex.org/S22130598","display_name":"Computer Science - Research and Development","issn_l":"1865-2034","issn":["1865-2034","1865-2042"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer Science - Research and Development","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064741703","display_name":"Michael Deisher","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Michael Deisher","raw_affiliation_strings":["Intel Labs, Hillsboro, OR, USA","Intel Laboratories, Hillsboro, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Labs, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Laboratories, Hillsboro, USA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007892541","display_name":"Mikhail Smelyanskiy","orcid":"https://orcid.org/0000-0002-2433-6110"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mikhail Smelyanskiy","raw_affiliation_strings":["Intel Labs, Santa Clara, CA, USA","Intel Labs,Santa Clara,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs,Santa Clara,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024943137","display_name":"Brian Nickerson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brian Nickerson","raw_affiliation_strings":["Intel Architecture Group, Santa Clara, CA, USA","Intel Architecture Group, Santa Clara, USA"],"affiliations":[{"raw_affiliation_string":"Intel Architecture Group, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Architecture Group, Santa Clara, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109971580","display_name":"Victor W. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Victor W. Lee","raw_affiliation_strings":["Intel Labs, Santa Clara, CA, USA","Intel Labs,Santa Clara,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs,Santa Clara,USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077370742","display_name":"Michael Chuvelev","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Michael Chuvelev","raw_affiliation_strings":["Software and Solutions Group, Nizhny Novgorod, Russia","Software and Solutions Group, Nizhny Novgorod, Russia#TAB#"],"affiliations":[{"raw_affiliation_string":"Software and Solutions Group, Nizhny Novgorod, Russia","institution_ids":[]},{"raw_affiliation_string":"Software and Solutions Group, Nizhny Novgorod, Russia#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032238070","display_name":"Pradeep Dubey","orcid":"https://orcid.org/0000-0001-5853-0619"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pradeep Dubey","raw_affiliation_strings":["Intel Labs, Santa Clara, CA, USA","Intel Labs,Santa Clara,USA"],"affiliations":[{"raw_affiliation_string":"Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs,Santa Clara,USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5064741703"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":5.4355,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.96210644,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"26","issue":"3-4","first_page":"211","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.8355187177658081},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8329548835754395},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6830384731292725},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.5901237726211548},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.5605131983757019},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.522742509841919},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5198781490325928},{"id":"https://openalex.org/keywords/load-balancing","display_name":"Load balancing (electrical power)","score":0.41260018944740295},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36750632524490356},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3346726894378662}],"concepts":[{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.8355187177658081},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8329548835754395},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6830384731292725},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.5901237726211548},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.5605131983757019},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.522742509841919},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5198781490325928},{"id":"https://openalex.org/C138959212","wikidata":"https://www.wikidata.org/wiki/Q1806783","display_name":"Load balancing (electrical power)","level":3,"score":0.41260018944740295},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36750632524490356},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3346726894378662},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C187691185","wikidata":"https://www.wikidata.org/wiki/Q2020720","display_name":"Grid","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00450-011-0169-x","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00450-011-0169-x","pdf_url":null,"source":{"id":"https://openalex.org/S22130598","display_name":"Computer Science - Research and Development","issn_l":"1865-2034","issn":["1865-2034","1865-2042"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Computer Science - Research and Development","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320332749","display_name":"University of Massachusetts Amherst","ror":"https://ror.org/0072zz521"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1552224009","https://openalex.org/W1568272005","https://openalex.org/W1991133427","https://openalex.org/W2016279572","https://openalex.org/W2047614366","https://openalex.org/W2047656763","https://openalex.org/W2063186542","https://openalex.org/W2124480634","https://openalex.org/W2162322364","https://openalex.org/W2163688235","https://openalex.org/W2169150754","https://openalex.org/W2798909945"],"related_works":["https://openalex.org/W2213533160","https://openalex.org/W4252450863","https://openalex.org/W2467043670","https://openalex.org/W187726678","https://openalex.org/W2051078434","https://openalex.org/W2085105049","https://openalex.org/W3203561460","https://openalex.org/W2682544458","https://openalex.org/W3009624197","https://openalex.org/W4251138667"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":12},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}