{"id":"https://openalex.org/W4412793821","doi":"https://doi.org/10.1007/s00034-025-03273-9","title":"Multi-mode Power Gating to Reduce Current Ramp of Logic Circuit","display_name":"Multi-mode Power Gating to Reduce Current Ramp of Logic Circuit","publication_year":2025,"publication_date":"2025-07-31","ids":{"openalex":"https://openalex.org/W4412793821","doi":"https://doi.org/10.1007/s00034-025-03273-9"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-025-03273-9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-025-03273-9","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082215420","display_name":"Vijay Pratap Yadav","orcid":"https://orcid.org/0000-0003-4827-6412"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Vijay Pratap Yadav","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101511627","display_name":"Vipin Singh","orcid":"https://orcid.org/0000-0003-0312-0449"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vipin Kumar Singh","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065512661","display_name":"Sanjeev Kumar Metya","orcid":"https://orcid.org/0000-0003-4093-5639"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sanjeev Kumar Metya","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009067589","display_name":"Alak Majumder","orcid":"https://orcid.org/0000-0003-4775-8591"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Alak Majumder","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Lab, Department of Electronics& Communication Engineering, National Institute of Technology Arunachal Pradesh, Jote, 791113, India","institution_ids":["https://openalex.org/I57496824"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5082215420"],"corresponding_institution_ids":["https://openalex.org/I57496824"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17837778,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"44","issue":"12","first_page":"8941","last_page":"8966"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.7928919792175293},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.6020298004150391},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5945558547973633},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5148833990097046},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4658214747905731},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.4518987834453583},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.44423040747642517},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3974055051803589},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3752375543117523},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.303162157535553},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25701624155044556},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17024728655815125},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1280435025691986}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.7928919792175293},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.6020298004150391},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5945558547973633},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5148833990097046},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4658214747905731},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.4518987834453583},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.44423040747642517},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3974055051803589},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3752375543117523},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.303162157535553},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25701624155044556},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17024728655815125},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1280435025691986},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-025-03273-9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-025-03273-9","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1982515552","https://openalex.org/W2039097694","https://openalex.org/W2042352336","https://openalex.org/W2067039297","https://openalex.org/W2098194061","https://openalex.org/W2114621701","https://openalex.org/W2121225064","https://openalex.org/W2126416778","https://openalex.org/W2157504143","https://openalex.org/W2164794461","https://openalex.org/W2895676248","https://openalex.org/W2901347942","https://openalex.org/W3061280797","https://openalex.org/W3088383297","https://openalex.org/W3184607818","https://openalex.org/W4294068511","https://openalex.org/W4384159647","https://openalex.org/W4410153764","https://openalex.org/W4412604665"],"related_works":["https://openalex.org/W2259094912","https://openalex.org/W1987649265","https://openalex.org/W2371329481","https://openalex.org/W2049889603","https://openalex.org/W2136406454","https://openalex.org/W2061966795","https://openalex.org/W2171305391","https://openalex.org/W2056314744","https://openalex.org/W2171302144","https://openalex.org/W2078703397"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-12-01T21:03:38.442747","created_date":"2025-10-10T00:00:00"}
