{"id":"https://openalex.org/W4413840321","doi":"https://doi.org/10.1007/s00034-025-03268-6","title":"An 0.1\u00a0mm2/Ch 40\u00a0nm-CMOS 32-Channel Analog Front-End Acquisition Circuit with Analog-Domain Real-Time Offset Reduction and SS-ADC for LFP Neural Signal Recording","display_name":"An 0.1\u00a0mm2/Ch 40\u00a0nm-CMOS 32-Channel Analog Front-End Acquisition Circuit with Analog-Domain Real-Time Offset Reduction and SS-ADC for LFP Neural Signal Recording","publication_year":2025,"publication_date":"2025-08-30","ids":{"openalex":"https://openalex.org/W4413840321","doi":"https://doi.org/10.1007/s00034-025-03268-6"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-025-03268-6","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-025-03268-6","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101323257","display_name":"Xiaokun Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaokun Lin","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053103595","display_name":"Bin Wang","orcid":"https://orcid.org/0000-0003-0225-9393"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bin Wang","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100396572","display_name":"Lu Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lu Liu","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101907296","display_name":"Xingchen Zhou","orcid":"https://orcid.org/0000-0002-5700-2942"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xingchen Zhou","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019365851","display_name":"Weitao Yang","orcid":"https://orcid.org/0000-0001-5576-2828"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weitao Yang","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110732681","display_name":"Hong Wang","orcid":"https://orcid.org/0009-0008-9983-3825"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi\u2019an, 710071, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"State Key Laboratory of Wide Bandgap Semiconductor Technology, Faculty of Integrated Circuit, Xidian University, Xi'an, 710071, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5101323257"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.2237839,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"45","issue":"1","first_page":"254","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7422332763671875},{"id":"https://openalex.org/keywords/analog-front-end","display_name":"Analog front-end","score":0.641983687877655},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.583322286605835},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5778273940086365},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.48223432898521423},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.47463592886924744},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.46167516708374023},{"id":"https://openalex.org/keywords/analog-signal-processing","display_name":"Analog signal processing","score":0.43490588665008545},{"id":"https://openalex.org/keywords/analogue-switch","display_name":"Analogue switch","score":0.4322209060192108},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.42739230394363403},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39784955978393555},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.36732104420661926},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3291371166706085},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31785500049591064},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3081499934196472},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.28863370418548584},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.2352094054222107},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.2212267816066742},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17578640580177307},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17521753907203674},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.09032696485519409}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7422332763671875},{"id":"https://openalex.org/C2778870119","wikidata":"https://www.wikidata.org/wiki/Q16002927","display_name":"Analog front-end","level":3,"score":0.641983687877655},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.583322286605835},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5778273940086365},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.48223432898521423},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.47463592886924744},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.46167516708374023},{"id":"https://openalex.org/C379707","wikidata":"https://www.wikidata.org/wiki/Q2328303","display_name":"Analog signal processing","level":4,"score":0.43490588665008545},{"id":"https://openalex.org/C45367353","wikidata":"https://www.wikidata.org/wiki/Q1327315","display_name":"Analogue switch","level":3,"score":0.4322209060192108},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.42739230394363403},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39784955978393555},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.36732104420661926},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3291371166706085},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31785500049591064},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3081499934196472},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.28863370418548584},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.2352094054222107},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2212267816066742},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17578640580177307},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17521753907203674},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.09032696485519409},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-025-03268-6","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-025-03268-6","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1422049004","https://openalex.org/W1965291684","https://openalex.org/W2027087041","https://openalex.org/W2032268434","https://openalex.org/W2065682167","https://openalex.org/W2075135661","https://openalex.org/W2108560657","https://openalex.org/W2109472370","https://openalex.org/W2152776190","https://openalex.org/W2152963787","https://openalex.org/W2159318368","https://openalex.org/W2161390912","https://openalex.org/W2169766445","https://openalex.org/W2211705316","https://openalex.org/W2406533156","https://openalex.org/W2478721325","https://openalex.org/W2614364230","https://openalex.org/W2765737812","https://openalex.org/W2791759922","https://openalex.org/W2801295417","https://openalex.org/W2802631554","https://openalex.org/W2944787947","https://openalex.org/W2945758480","https://openalex.org/W2985457504","https://openalex.org/W2993973410","https://openalex.org/W3004729186","https://openalex.org/W3015809619","https://openalex.org/W3109811756","https://openalex.org/W4211203319","https://openalex.org/W4226409861","https://openalex.org/W4294904400","https://openalex.org/W4366579939","https://openalex.org/W4386432204"],"related_works":["https://openalex.org/W2044654414","https://openalex.org/W56967924","https://openalex.org/W2774445564","https://openalex.org/W4309264833","https://openalex.org/W2007222089","https://openalex.org/W1594014749","https://openalex.org/W2052627894","https://openalex.org/W2077138012","https://openalex.org/W3000964676","https://openalex.org/W2154287692"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-02-03T23:48:18.283914","created_date":"2025-10-10T00:00:00"}
