{"id":"https://openalex.org/W4405706694","doi":"https://doi.org/10.1007/s00034-024-02963-0","title":"An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC","display_name":"An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC","publication_year":2024,"publication_date":"2024-12-23","ids":{"openalex":"https://openalex.org/W4405706694","doi":"https://doi.org/10.1007/s00034-024-02963-0"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-024-02963-0","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s00034-024-02963-0","pdf_url":"https://link.springer.com/content/pdf/10.1007/s00034-024-02963-0.pdf","source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://link.springer.com/content/pdf/10.1007/s00034-024-02963-0.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091746415","display_name":"Shuowei Li","orcid":"https://orcid.org/0000-0002-0922-9755"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Shuowei Li","raw_affiliation_strings":["Department of Electrical Engineering and Information System, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan"],"raw_orcid":"https://orcid.org/0000-0002-0922-9755","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information System, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083782865","display_name":"Zunsong Yang","orcid":"https://orcid.org/0000-0001-8539-8481"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Zunsong Yang","raw_affiliation_strings":["Systems Design Laboratory, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Systems Design Laboratory, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007028121","display_name":"Tetsuya Iizuka","orcid":"https://orcid.org/0000-0002-1512-4714"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Tetsuya Iizuka","raw_affiliation_strings":["Systems Design Laboratory, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Systems Design Laboratory, School of Engineering, The University of Tokyo, Hongo, Bunkyo, Tokyo, 113-0032, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5007028121","https://openalex.org/A5091746415"],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.4548,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.60276129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"44","issue":"5","first_page":"2956","last_page":"2978"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6216788291931152},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.5412383675575256},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.4794436991214752},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40441417694091797},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.38592690229415894},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27277663350105286},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2439832091331482},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17230156064033508},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.16844066977500916}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6216788291931152},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.5412383675575256},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.4794436991214752},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40441417694091797},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.38592690229415894},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27277663350105286},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2439832091331482},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17230156064033508},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.16844066977500916}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-024-02963-0","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s00034-024-02963-0","pdf_url":"https://link.springer.com/content/pdf/10.1007/s00034-024-02963-0.pdf","source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1007/s00034-024-02963-0","is_oa":true,"landing_page_url":"https://doi.org/10.1007/s00034-024-02963-0","pdf_url":"https://link.springer.com/content/pdf/10.1007/s00034-024-02963-0.pdf","source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1216449390","display_name":"Establishing a Platform for Inter-Chip Communication Technology Using Dielectric Waveguides for Large-Scale AI Systems","funder_award_id":"21H03406","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"},{"id":"https://openalex.org/G2723994578","display_name":null,"funder_award_id":"JP21H03406","funder_id":"https://openalex.org/F4320334764","funder_display_name":"Japan Society for the Promotion of Science"},{"id":"https://openalex.org/G335507868","display_name":null,"funder_award_id":"JPMJTR201C","funder_id":"https://openalex.org/F4320338117","funder_display_name":"Adaptable and Seamless Technology Transfer Program through Target-Driven R and D"}],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"},{"id":"https://openalex.org/F4320334764","display_name":"Japan Society for the Promotion of Science","ror":"https://ror.org/00hhkn466"},{"id":"https://openalex.org/F4320338117","display_name":"Adaptable and Seamless Technology Transfer Program through Target-Driven R and D","ror":null}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4405706694.pdf","grobid_xml":"https://content.openalex.org/works/W4405706694.grobid-xml"},"referenced_works_count":23,"referenced_works":["https://openalex.org/W1969925016","https://openalex.org/W1983740965","https://openalex.org/W2019720625","https://openalex.org/W2022847884","https://openalex.org/W2140903142","https://openalex.org/W2152208424","https://openalex.org/W2537738414","https://openalex.org/W2790701163","https://openalex.org/W2791757449","https://openalex.org/W2795591835","https://openalex.org/W2891288687","https://openalex.org/W2897351503","https://openalex.org/W2918730494","https://openalex.org/W2943848730","https://openalex.org/W3001307815","https://openalex.org/W3016114585","https://openalex.org/W3045068248","https://openalex.org/W3154289504","https://openalex.org/W3209003531","https://openalex.org/W4223966183","https://openalex.org/W4235645058","https://openalex.org/W4285208820","https://openalex.org/W4312690233"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W3102847316","https://openalex.org/W3172386668","https://openalex.org/W2390279801","https://openalex.org/W3011006018","https://openalex.org/W2981692717","https://openalex.org/W4386571252","https://openalex.org/W4391913857"],"abstract_inverted_index":{"Abstract":[0],"This":[1],"paper":[2],"proposes":[3],"an":[4,47,53],"8-bit":[5],"synthesizable":[6],"SAR":[7],"ADC":[8,48],"with":[9,49],"inverter-cell-based":[10,16,54],"capacitive":[11],"digital-to-analog":[12],"converters":[13],"(CDACs).":[14],"An":[15],"capacitor":[17],"is":[18,57,78,115],"proposed":[19,58],"by":[20],"connecting":[21],"the":[22,28,38,96,132],"supply":[23],"and":[24,64,98,103],"ground":[25],"ports":[26],"of":[27,135],"inverter":[29],"cells":[30],"together":[31],"but":[32],"leaving":[33],"them":[34],"floated":[35],"to":[36,41,59,66,131],"suppress":[37],"voltage":[39],"dependence":[40],"be":[42,60],"suitable":[43],"for":[44],"employment":[45],"in":[46,62,80],"moderate":[50],"resolution.":[51],"Furthermore,":[52],"analog":[55],"switch":[56],"employed":[61],"S/H":[63],"CDAC":[65],"achieve":[67],"a":[68,81,93,125],"fully":[69],"standard-cell-based":[70],"design":[71],"without":[72,110],"any":[73],"custom-designed":[74],"cells.":[75],"The":[76,112],"prototype":[77],"fabricated":[79],"65":[82],"nm":[83],"standard":[84],"CMOS":[85],"process":[86],"occupying":[87],"0.19":[88],"mm":[89],"2":[90],".":[91],"With":[92],"Nyquist":[94],"input,":[95],"SFDR":[97],"SNDR":[99],"reach":[100],"53.6":[101],"dB":[102,105],"46.2":[104],"at":[106],"2.92":[107],"MS/s":[108],"respectively":[109],"calibration.":[111],"power":[113],"consumption":[114],"425":[116],"$${\\mu":[117],"}$$":[118],"<mml:math":[119],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\">":[120],"<mml:mi>\u03bc</mml:mi>":[121],"</mml:math>":[122],"W":[123],"from":[124],"1.2":[126],"V":[127],"supply,":[128],"which":[129],"leads":[130],"Walden":[133],"FoM":[134],"0.86":[136],"pJ/conv.-step.":[137]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-13T06:13:01.061226","created_date":"2025-10-10T00:00:00"}
