{"id":"https://openalex.org/W4405358685","doi":"https://doi.org/10.1007/s00034-024-02949-y","title":"High Performance MAC Unit Design with Grouping and Decomposition Multiplier and 18\u00a0T Gate Diffusion Input-Transmission Gate Adder","display_name":"High Performance MAC Unit Design with Grouping and Decomposition Multiplier and 18\u00a0T Gate Diffusion Input-Transmission Gate Adder","publication_year":2024,"publication_date":"2024-12-13","ids":{"openalex":"https://openalex.org/W4405358685","doi":"https://doi.org/10.1007/s00034-024-02949-y"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-024-02949-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-024-02949-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101862460","display_name":"S. Umadevi","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"S. Umadevi","raw_affiliation_strings":["Centre for Nanoelectronics and VLSI Design, VIT University, Chennai Campus, Chennai, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"Centre for Nanoelectronics and VLSI Design, VIT University, Chennai Campus, Chennai, Tamilnadu, India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115427779","display_name":"Punith Penumaka","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Punith Penumaka","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai Campus, Chennai, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai Campus, Chennai, Tamilnadu, India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012813875","display_name":"Chaina Ram","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"C. Koushik Ram","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai Campus, Chennai, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai Campus, Chennai, Tamilnadu, India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054404522","display_name":"T. Kalavathi Devi","orcid":"https://orcid.org/0000-0003-3356-6601"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Kalavathi Devi","raw_affiliation_strings":["Department of EIE, Kongu Engineering College, Perundurai, Erode, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"Department of EIE, Kongu Engineering College, Perundurai, Erode, Tamilnadu, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5101862460"],"corresponding_institution_ids":["https://openalex.org/I876193797"],"apc_list":null,"apc_paid":null,"fwci":0.8666,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75089735,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"44","issue":"4","first_page":"2830","last_page":"2854"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8286187648773193},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.7276363372802734},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5894754528999329},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5788043737411499},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.4521621763706207},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.4330362379550934},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42085713148117065},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.41319990158081055},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4005180597305298},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33736276626586914},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3212318420410156},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23541277647018433},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19014090299606323},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1605975329875946},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1394597589969635},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1376895010471344},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10667729377746582}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8286187648773193},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.7276363372802734},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5894754528999329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5788043737411499},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.4521621763706207},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.4330362379550934},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42085713148117065},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.41319990158081055},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4005180597305298},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33736276626586914},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3212318420410156},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23541277647018433},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19014090299606323},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1605975329875946},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1394597589969635},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1376895010471344},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10667729377746582},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-024-02949-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-024-02949-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1823439865","https://openalex.org/W2025315299","https://openalex.org/W2113734214","https://openalex.org/W2129278962","https://openalex.org/W2289252105","https://openalex.org/W2296712544","https://openalex.org/W2521912036","https://openalex.org/W2545920993","https://openalex.org/W2604319603","https://openalex.org/W2611106620","https://openalex.org/W2783649626","https://openalex.org/W2788490660","https://openalex.org/W2788882849","https://openalex.org/W2791337398","https://openalex.org/W2795961274","https://openalex.org/W2894853537","https://openalex.org/W2913719236","https://openalex.org/W2948850835","https://openalex.org/W2974263490","https://openalex.org/W2980172915","https://openalex.org/W3010038952","https://openalex.org/W3104899488","https://openalex.org/W3139420624","https://openalex.org/W3163420603","https://openalex.org/W3169000237","https://openalex.org/W3170539473","https://openalex.org/W4225880954","https://openalex.org/W4306818531","https://openalex.org/W4313287839","https://openalex.org/W4387816817"],"related_works":["https://openalex.org/W2187717486","https://openalex.org/W1861470194","https://openalex.org/W2912120797","https://openalex.org/W4320030318","https://openalex.org/W2128096982","https://openalex.org/W2778612236","https://openalex.org/W2807717303","https://openalex.org/W2007403364","https://openalex.org/W2977485606","https://openalex.org/W2130293049"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
