{"id":"https://openalex.org/W4205313707","doi":"https://doi.org/10.1007/s00034-021-01873-9","title":"BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator","display_name":"BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator","publication_year":2022,"publication_date":"2022-01-08","ids":{"openalex":"https://openalex.org/W4205313707","doi":"https://doi.org/10.1007/s00034-021-01873-9"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-021-01873-9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-021-01873-9","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061735339","display_name":"Harsh Chhajed","orcid":"https://orcid.org/0009-0008-7055-7740"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Harsh Chhajed","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028707436","display_name":"Gopal Raut","orcid":"https://orcid.org/0000-0002-1046-9457"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gopal Raut","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010528437","display_name":"Narendra Singh Dhakad","orcid":"https://orcid.org/0000-0003-2848-1785"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Narendra Dhakad","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113969405","display_name":"Sudheer Vishwakarma","orcid":null},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudheer Vishwakarma","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068792760","display_name":"Santosh Kumar Vishvakarma","orcid":"https://orcid.org/0000-0003-4223-0077"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santosh Kumar Vishvakarma","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Indore, 453552, Simrol, India","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5061735339"],"corresponding_institution_ids":["https://openalex.org/I64295750"],"apc_list":null,"apc_paid":null,"fwci":1.567,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.8191186,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"41","issue":"4","first_page":"2045","last_page":"2060"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6925069689750671},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5527341961860657},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5037032961845398},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4981858730316162},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4844963252544403},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46939390897750854},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4196087121963501},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.21938422322273254},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.184209942817688},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16441738605499268},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15484407544136047}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6925069689750671},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5527341961860657},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5037032961845398},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4981858730316162},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4844963252544403},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46939390897750854},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4196087121963501},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.21938422322273254},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.184209942817688},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16441738605499268},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15484407544136047},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-021-01873-9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-021-01873-9","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2857725320","display_name":null,"funder_award_id":"22745/Dec2015","funder_id":"https://openalex.org/F4320335491","funder_display_name":"UGC-DAE\u00a0Consortium for Scientific Research, University Grants Commission"}],"funders":[{"id":"https://openalex.org/F4320335491","display_name":"UGC-DAE\u00a0Consortium for Scientific Research, University Grants Commission","ror":"https://ror.org/047g7f905"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1605005685","https://openalex.org/W1975112218","https://openalex.org/W1999798000","https://openalex.org/W2299244345","https://openalex.org/W2527036487","https://openalex.org/W2555599679","https://openalex.org/W2565125333","https://openalex.org/W2734851905","https://openalex.org/W2771877514","https://openalex.org/W2773033565","https://openalex.org/W2792007352","https://openalex.org/W2802831927","https://openalex.org/W2883340368","https://openalex.org/W2887669960","https://openalex.org/W2902026820","https://openalex.org/W2942493598","https://openalex.org/W2963367920","https://openalex.org/W2967632137","https://openalex.org/W2972588912","https://openalex.org/W2974204398","https://openalex.org/W2985727781","https://openalex.org/W3004524066","https://openalex.org/W3036119011","https://openalex.org/W3047364742","https://openalex.org/W3124625166","https://openalex.org/W3160282718","https://openalex.org/W4247198796","https://openalex.org/W6609417632"],"related_works":["https://openalex.org/W17155033","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W1590307681","https://openalex.org/W4312814274","https://openalex.org/W4285370786","https://openalex.org/W2296488620","https://openalex.org/W2358353312","https://openalex.org/W2353836703","https://openalex.org/W41015297"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}