{"id":"https://openalex.org/W3021265112","doi":"https://doi.org/10.1007/s00034-020-01411-z","title":"An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks","display_name":"An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks","publication_year":2020,"publication_date":"2020-05-04","ids":{"openalex":"https://openalex.org/W3021265112","doi":"https://doi.org/10.1007/s00034-020-01411-z","mag":"3021265112"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-020-01411-z","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-020-01411-z","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014104140","display_name":"B. M. Prabhu Prasad","orcid":"https://orcid.org/0000-0002-6138-3012"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"B. M. Prabhu\u00a0Prasad","raw_affiliation_strings":["SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India"],"affiliations":[{"raw_affiliation_string":"SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India","institution_ids":["https://openalex.org/I11880225"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079634639","display_name":"Khyamling Parane","orcid":"https://orcid.org/0000-0003-4176-4640"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Khyamling Parane","raw_affiliation_strings":["SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India"],"affiliations":[{"raw_affiliation_string":"SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India","institution_ids":["https://openalex.org/I11880225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004440264","display_name":"Basavaraj Talawar","orcid":"https://orcid.org/0000-0001-5054-3124"},"institutions":[{"id":"https://openalex.org/I11880225","display_name":"National Institute of Technology Karnataka","ror":"https://ror.org/01hz4v948","country_code":"IN","type":"education","lineage":["https://openalex.org/I11880225"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Basavaraj Talawar","raw_affiliation_strings":["SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India"],"affiliations":[{"raw_affiliation_string":"SPARK Lab, Department of CSE, National Institute of Technology Karnataka Surathkal, Mangalore, India","institution_ids":["https://openalex.org/I11880225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5014104140"],"corresponding_institution_ids":["https://openalex.org/I11880225"],"apc_list":null,"apc_paid":null,"fwci":0.8058,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.74632117,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"39","issue":"10","first_page":"5247","last_page":"5271"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.9211962223052979},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7235382199287415},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.703536331653595},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6026093363761902},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5576589703559875},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5460377931594849},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5439361333847046},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.524584949016571},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5194156169891357},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4676028788089752},{"id":"https://openalex.org/keywords/mesh-networking","display_name":"Mesh networking","score":0.46244627237319946},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39681094884872437},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3927202522754669},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3673999309539795},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.29991817474365234},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.20541197061538696},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16226187348365784},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.0893450677394867},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08743438124656677}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.9211962223052979},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7235382199287415},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.703536331653595},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6026093363761902},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5576589703559875},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5460377931594849},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5439361333847046},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.524584949016571},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5194156169891357},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4676028788089752},{"id":"https://openalex.org/C123691950","wikidata":"https://www.wikidata.org/wiki/Q25552104","display_name":"Mesh networking","level":3,"score":0.46244627237319946},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39681094884872437},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3927202522754669},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3673999309539795},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.29991817474365234},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.20541197061538696},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16226187348365784},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0893450677394867},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08743438124656677},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-020-01411-z","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-020-01411-z","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G739109230","display_name":null,"funder_award_id":"DIC/MUM/GA/10(37)D","funder_id":"https://openalex.org/F4320321071","funder_display_name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology"}],"funders":[{"id":"https://openalex.org/F4320321071","display_name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology","ror":"https://ror.org/02z31cn83"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1644436786","https://openalex.org/W1651994298","https://openalex.org/W2016465432","https://openalex.org/W2021124483","https://openalex.org/W2046422371","https://openalex.org/W2059462720","https://openalex.org/W2077505860","https://openalex.org/W2099917528","https://openalex.org/W2108436158","https://openalex.org/W2118231264","https://openalex.org/W2123184444","https://openalex.org/W2123901034","https://openalex.org/W2128402381","https://openalex.org/W2130183852","https://openalex.org/W2134736689","https://openalex.org/W2157225945","https://openalex.org/W2162292936","https://openalex.org/W2163061018","https://openalex.org/W2204870480","https://openalex.org/W2524701127","https://openalex.org/W2526108948","https://openalex.org/W2795260458","https://openalex.org/W2941940564","https://openalex.org/W6602452458","https://openalex.org/W6605817598","https://openalex.org/W6631644673","https://openalex.org/W6738317309","https://openalex.org/W6832598095"],"related_works":["https://openalex.org/W2352167000","https://openalex.org/W3038685860","https://openalex.org/W2576538540","https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2603824091","https://openalex.org/W2439487276","https://openalex.org/W2560886726","https://openalex.org/W2510977931","https://openalex.org/W2541438272"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}