{"id":"https://openalex.org/W2949508004","doi":"https://doi.org/10.1007/s00034-019-01163-5","title":"Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems","display_name":"Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems","publication_year":2019,"publication_date":"2019-06-11","ids":{"openalex":"https://openalex.org/W2949508004","doi":"https://doi.org/10.1007/s00034-019-01163-5","mag":"2949508004"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-019-01163-5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-019-01163-5","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044921376","display_name":"Jiang En-hua","orcid":null},"institutions":[{"id":"https://openalex.org/I165859042","display_name":"Huaibei Normal University","ror":"https://ror.org/03ek23472","country_code":"CN","type":"education","lineage":["https://openalex.org/I165859042"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"En-hua Jiang","raw_affiliation_strings":["School of Physics and Electronic Information, Huaibei Normal University, Huaibei, 235000, Anhui, China"],"affiliations":[{"raw_affiliation_string":"School of Physics and Electronic Information, Huaibei Normal University, Huaibei, 235000, Anhui, China","institution_ids":["https://openalex.org/I165859042"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101489519","display_name":"Wenbin Jiang","orcid":"https://orcid.org/0009-0001-6191-1102"},"institutions":[{"id":"https://openalex.org/I165859042","display_name":"Huaibei Normal University","ror":"https://ror.org/03ek23472","country_code":"CN","type":"education","lineage":["https://openalex.org/I165859042"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wen-bin Jiang","raw_affiliation_strings":["School of Physics and Electronic Information, Huaibei Normal University, Huaibei, 235000, Anhui, China"],"affiliations":[{"raw_affiliation_string":"School of Physics and Electronic Information, Huaibei Normal University, Huaibei, 235000, Anhui, China","institution_ids":["https://openalex.org/I165859042"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5044921376"],"corresponding_institution_ids":["https://openalex.org/I165859042"],"apc_list":null,"apc_paid":null,"fwci":0.1205,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.44975833,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"38","issue":"12","first_page":"5817","last_page":"5838"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6764026284217834},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5884159803390503},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5363520383834839},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5308011174201965},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5225222110748291},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5127063989639282},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5093525648117065},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48300206661224365},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.4636576771736145},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4597179889678955},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4412873685359955},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4030904173851013},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.34019529819488525},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2070145606994629},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19450822472572327},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1829773187637329}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6764026284217834},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5884159803390503},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5363520383834839},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5308011174201965},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5225222110748291},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5127063989639282},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5093525648117065},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48300206661224365},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.4636576771736145},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4597179889678955},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4412873685359955},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4030904173851013},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.34019529819488525},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2070145606994629},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19450822472572327},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1829773187637329}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-019-01163-5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-019-01163-5","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1882870471","https://openalex.org/W1966341793","https://openalex.org/W1994627436","https://openalex.org/W2000462061","https://openalex.org/W2009985530","https://openalex.org/W2046103068","https://openalex.org/W2098769011","https://openalex.org/W2113192550","https://openalex.org/W2124278579","https://openalex.org/W2125546921","https://openalex.org/W2138968074","https://openalex.org/W2141849037","https://openalex.org/W2168491240","https://openalex.org/W2507870178","https://openalex.org/W2803057706","https://openalex.org/W3174540764"],"related_works":["https://openalex.org/W1494292626","https://openalex.org/W3217430545","https://openalex.org/W2083793411","https://openalex.org/W1532891187","https://openalex.org/W2765435638","https://openalex.org/W6024065","https://openalex.org/W2178512053","https://openalex.org/W2350960814","https://openalex.org/W2112242076","https://openalex.org/W4242766712"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}