{"id":"https://openalex.org/W2897677202","doi":"https://doi.org/10.1007/s00034-018-0953-y","title":"A Reconfigurable Hardware Architecture for Principal Component Analysis","display_name":"A Reconfigurable Hardware Architecture for Principal Component Analysis","publication_year":2018,"publication_date":"2018-10-10","ids":{"openalex":"https://openalex.org/W2897677202","doi":"https://doi.org/10.1007/s00034-018-0953-y","mag":"2897677202"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-018-0953-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-018-0953-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062812229","display_name":"Uday A. Korat","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Uday A. Korat","raw_affiliation_strings":["Intel Inc., Folsom, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Inc., Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082698655","display_name":"Amirhossein Alimohammad","orcid":"https://orcid.org/0000-0002-0265-0774"},"institutions":[{"id":"https://openalex.org/I26538001","display_name":"San Diego State University","ror":"https://ror.org/0264fdx42","country_code":"US","type":"education","lineage":["https://openalex.org/I26538001"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amirhossein Alimohammad","raw_affiliation_strings":["Department of Electrical and Computer Engineering, San Diego State University, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, San Diego State University, San Diego, CA, USA","institution_ids":["https://openalex.org/I26538001"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5062812229"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.6684,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.68311343,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"38","issue":"5","first_page":"2097","last_page":"2113"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11236","display_name":"Control Systems and Identification","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8199150562286377},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7506216764450073},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6477599143981934},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5627402663230896},{"id":"https://openalex.org/keywords/principal-component-analysis","display_name":"Principal component analysis","score":0.5068894028663635},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.48871755599975586},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4784531593322754},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4500584304332733},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42247113585472107},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.4162661135196686},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.4135338068008423},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3601841926574707},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.3003332018852234},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16277551651000977},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16275200247764587}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8199150562286377},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7506216764450073},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6477599143981934},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5627402663230896},{"id":"https://openalex.org/C27438332","wikidata":"https://www.wikidata.org/wiki/Q2873","display_name":"Principal component analysis","level":2,"score":0.5068894028663635},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.48871755599975586},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4784531593322754},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4500584304332733},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42247113585472107},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.4162661135196686},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.4135338068008423},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3601841926574707},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3003332018852234},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16277551651000977},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16275200247764587},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-018-0953-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-018-0953-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1608314685","https://openalex.org/W1973942615","https://openalex.org/W2044829853","https://openalex.org/W2062576624","https://openalex.org/W2065754136","https://openalex.org/W2105602969","https://openalex.org/W2112582768","https://openalex.org/W2122860281","https://openalex.org/W2128728535","https://openalex.org/W2152174305","https://openalex.org/W2165011274","https://openalex.org/W2284903658","https://openalex.org/W2418706253","https://openalex.org/W2623057063","https://openalex.org/W2782922042","https://openalex.org/W2798909945","https://openalex.org/W6600930449","https://openalex.org/W6601630192","https://openalex.org/W6601796474","https://openalex.org/W6601881253"],"related_works":["https://openalex.org/W2037154093","https://openalex.org/W2127392486","https://openalex.org/W3149845128","https://openalex.org/W2075931580","https://openalex.org/W1992393033","https://openalex.org/W2152652624","https://openalex.org/W2125591518","https://openalex.org/W2158082586","https://openalex.org/W2359192593","https://openalex.org/W2120461351"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":4}],"updated_date":"2026-04-04T06:10:10.580331","created_date":"2025-10-10T00:00:00"}