{"id":"https://openalex.org/W2790500346","doi":"https://doi.org/10.1007/s00034-018-0781-0","title":"Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network","display_name":"Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network","publication_year":2018,"publication_date":"2018-02-20","ids":{"openalex":"https://openalex.org/W2790500346","doi":"https://doi.org/10.1007/s00034-018-0781-0","mag":"2790500346"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-018-0781-0","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-018-0781-0","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102817544","display_name":"Amit Kumar Pandey","orcid":"https://orcid.org/0000-0002-4761-4646"},"institutions":[{"id":"https://openalex.org/I236004819","display_name":"Babasaheb Bhimrao Ambedkar Bihar University","ror":"https://ror.org/04jgpa018","country_code":"IN","type":"education","lineage":["https://openalex.org/I236004819"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Amit Kumar Pandey","raw_affiliation_strings":["Department of Applied Science, Rajkiya Engineering College, Ambedkar nagar, Akbarpur, Uttar Pradesh, 224122, India","Department of Applied Science, Rajkiya Engineering College, Akbarpur, India"],"affiliations":[{"raw_affiliation_string":"Department of Applied Science, Rajkiya Engineering College, Ambedkar nagar, Akbarpur, Uttar Pradesh, 224122, India","institution_ids":["https://openalex.org/I236004819"]},{"raw_affiliation_string":"Department of Applied Science, Rajkiya Engineering College, Akbarpur, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058680864","display_name":"Pawan Kumar Verma","orcid":"https://orcid.org/0000-0003-2754-6137"},"institutions":[{"id":"https://openalex.org/I70971781","display_name":"Dr. B. R. Ambedkar National Institute of Technology Jalandhar","ror":"https://ror.org/03xt0bg88","country_code":"IN","type":"education","lineage":["https://openalex.org/I70971781"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pawan Kumar Verma","raw_affiliation_strings":["Department of Electronics and Communication, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, 144011, India","Department of Electronics and Communication, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, 144011, India","institution_ids":["https://openalex.org/I70971781"]},{"raw_affiliation_string":"Department of Electronics and Communication, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, India","institution_ids":["https://openalex.org/I70971781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078906878","display_name":"Rajesh Verma","orcid":"https://orcid.org/0000-0002-7024-0216"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rajesh Verma","raw_affiliation_strings":["Department of Electronics and Communication, Raj Kumar Goel Institute of Technology and Management, Ghaziabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, Raj Kumar Goel Institute of Technology and Management, Ghaziabad, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033819723","display_name":"Tarun Kumar Gupta","orcid":"https://orcid.org/0000-0002-4335-1420"},"institutions":[{"id":"https://openalex.org/I91277730","display_name":"Maulana Azad National Institute of Technology","ror":"https://ror.org/026vtd268","country_code":"IN","type":"education","lineage":["https://openalex.org/I91277730"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tarun Kumar Gupta","raw_affiliation_strings":["Department of Electronics and Communication, Maulana Azad National Institute of Technology, Bhopal, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, Maulana Azad National Institute of Technology, Bhopal, India","institution_ids":["https://openalex.org/I91277730"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102817544"],"corresponding_institution_ids":["https://openalex.org/I236004819"],"apc_list":null,"apc_paid":null,"fwci":0.1303,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.45451608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"37","issue":"10","first_page":"4599","last_page":"4616"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7296014428138733},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.7185294032096863},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5713901519775391},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.558987021446228},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.479636013507843},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4692385494709015},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4580468535423279},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.44050782918930054},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4308726489543915},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4206274747848511},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.3943513035774231},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25557512044906616},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.23484885692596436},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21410304307937622}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7296014428138733},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.7185294032096863},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5713901519775391},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.558987021446228},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.479636013507843},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4692385494709015},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4580468535423279},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.44050782918930054},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4308726489543915},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4206274747848511},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3943513035774231},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25557512044906616},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.23484885692596436},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21410304307937622},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-018-0781-0","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-018-0781-0","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W625693296","https://openalex.org/W1590907107","https://openalex.org/W1597620877","https://openalex.org/W1771272854","https://openalex.org/W1882507454","https://openalex.org/W1934415477","https://openalex.org/W1987370976","https://openalex.org/W1988102072","https://openalex.org/W1992366201","https://openalex.org/W1997449957","https://openalex.org/W2027095146","https://openalex.org/W2039097694","https://openalex.org/W2043620677","https://openalex.org/W2045403765","https://openalex.org/W2083124406","https://openalex.org/W2096663360","https://openalex.org/W2110429304","https://openalex.org/W2125765139","https://openalex.org/W2127876484","https://openalex.org/W2134076376","https://openalex.org/W2135049527","https://openalex.org/W2140541049","https://openalex.org/W2142097710","https://openalex.org/W2146517200","https://openalex.org/W2150513440","https://openalex.org/W2156919792","https://openalex.org/W2158932653","https://openalex.org/W2166749966","https://openalex.org/W2168226525","https://openalex.org/W2173367578","https://openalex.org/W2185642762","https://openalex.org/W2536170432","https://openalex.org/W2568381411","https://openalex.org/W6600137863","https://openalex.org/W6605544024","https://openalex.org/W6633392134","https://openalex.org/W6640432219"],"related_works":["https://openalex.org/W754115298","https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W2891188466","https://openalex.org/W2150513440","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2098328611","https://openalex.org/W2100009051"],"abstract_inverted_index":null,"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}