{"id":"https://openalex.org/W2003488806","doi":"https://doi.org/10.1007/s00034-015-0020-x","title":"Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm","display_name":"Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm","publication_year":2015,"publication_date":"2015-03-14","ids":{"openalex":"https://openalex.org/W2003488806","doi":"https://doi.org/10.1007/s00034-015-0020-x","mag":"2003488806"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-015-0020-x","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-015-0020-x","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039582689","display_name":"P. Sivaranjani","orcid":"https://orcid.org/0000-0001-5500-6109"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Sivaranjani","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, 638052, Tamilnadu, India","Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, India 638052#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, 638052, Tamilnadu, India","institution_ids":[]},{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, India 638052#TAB#","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074285622","display_name":"A. Senthil Kumar","orcid":"https://orcid.org/0000-0002-8468-9348"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Senthil Kumar","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, 642003, Tamilnadu, India","Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, India 642003#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, 642003, Tamilnadu, India","institution_ids":[]},{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, India 642003#TAB#","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.205,"has_fulltext":false,"cited_by_count":34,"citation_normalized_percentile":{"value":0.816956,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"34","issue":"11","first_page":"3521","last_page":"3542"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.949522852897644},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5777820348739624},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5704285502433777},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5361416935920715},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5263553857803345},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5051072239875793},{"id":"https://openalex.org/keywords/particle-swarm-optimization","display_name":"Particle swarm optimization","score":0.49854516983032227},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4861864447593689},{"id":"https://openalex.org/keywords/slicing","display_name":"Slicing","score":0.48385488986968994},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.480160653591156},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4576927125453949},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.43489694595336914},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.4303855895996094},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.39575135707855225},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.34119483828544617},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.2830999791622162},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2328362762928009},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15926504135131836}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.949522852897644},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5777820348739624},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5704285502433777},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5361416935920715},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5263553857803345},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5051072239875793},{"id":"https://openalex.org/C85617194","wikidata":"https://www.wikidata.org/wiki/Q2072794","display_name":"Particle swarm optimization","level":2,"score":0.49854516983032227},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4861864447593689},{"id":"https://openalex.org/C2776190703","wikidata":"https://www.wikidata.org/wiki/Q488148","display_name":"Slicing","level":2,"score":0.48385488986968994},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.480160653591156},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4576927125453949},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.43489694595336914},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.4303855895996094},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.39575135707855225},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.34119483828544617},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2830999791622162},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2328362762928009},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15926504135131836},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-015-0020-x","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-015-0020-x","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1501388320","https://openalex.org/W1969484022","https://openalex.org/W1971316310","https://openalex.org/W1973235702","https://openalex.org/W1980278167","https://openalex.org/W1989874002","https://openalex.org/W1992171695","https://openalex.org/W1997840407","https://openalex.org/W2025516544","https://openalex.org/W2029631366","https://openalex.org/W2051735556","https://openalex.org/W2062763943","https://openalex.org/W2097543269","https://openalex.org/W2100404320","https://openalex.org/W2104086123","https://openalex.org/W2106122737","https://openalex.org/W2107506931","https://openalex.org/W2109826730","https://openalex.org/W2114772983","https://openalex.org/W2116670216","https://openalex.org/W2119408963","https://openalex.org/W2122245206","https://openalex.org/W2129355781","https://openalex.org/W2147005738","https://openalex.org/W2148777220","https://openalex.org/W2152150600","https://openalex.org/W2157315754","https://openalex.org/W2883512297","https://openalex.org/W2904250082","https://openalex.org/W3023540311","https://openalex.org/W6634681119"],"related_works":["https://openalex.org/W2157271968","https://openalex.org/W2158448234","https://openalex.org/W2004655383","https://openalex.org/W1523582517","https://openalex.org/W1984375234","https://openalex.org/W2115502122","https://openalex.org/W2138401961","https://openalex.org/W2162365765","https://openalex.org/W2353155791","https://openalex.org/W2109972882"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":5},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
