{"id":"https://openalex.org/W2048438719","doi":"https://doi.org/10.1007/s00034-013-9688-y","title":"Designing Dynamic Carry Skip Adders: Analysis and Comparison","display_name":"Designing Dynamic Carry Skip Adders: Analysis and Comparison","publication_year":2013,"publication_date":"2013-10-31","ids":{"openalex":"https://openalex.org/W2048438719","doi":"https://doi.org/10.1007/s00034-013-9688-y","mag":"2048438719"},"language":"en","primary_location":{"id":"doi:10.1007/s00034-013-9688-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-013-9688-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002197998","display_name":"Raffaele De Rose","orcid":"https://orcid.org/0000-0003-1184-1721"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Raffaele De Rose","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","University of Calabria"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"University of Calabria","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016654766","display_name":"Marco Lanuzza","orcid":"https://orcid.org/0000-0002-6480-9218"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Lanuzza","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","University of Calabria"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"University of Calabria","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011214102","display_name":"Fabio Frustaci","orcid":"https://orcid.org/0000-0001-5795-4321"},"institutions":[{"id":"https://openalex.org/I45204951","display_name":"University of Calabria","ror":"https://ror.org/02rc97e94","country_code":"IT","type":"education","lineage":["https://openalex.org/I45204951"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabio Frustaci","raw_affiliation_strings":["Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","University of Calabria"],"affiliations":[{"raw_affiliation_string":"Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Via P. Bucci 42C, 87036, Arcavacata Di Rende, CS, Italy","institution_ids":["https://openalex.org/I45204951"]},{"raw_affiliation_string":"University of Calabria","institution_ids":["https://openalex.org/I45204951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109104631","display_name":"Sohan Purohit","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Sohan Purohit","raw_affiliation_strings":["Intel Corporation, Austin, TX, 78746, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Austin, TX, 78746, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5002197998"],"corresponding_institution_ids":["https://openalex.org/I45204951"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.1100133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"33","issue":"4","first_page":"1019","last_page":"1034"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9020317196846008},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.6563780307769775},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6541893482208252},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.5825543403625488},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.5207481384277344},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4759904146194458},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.456709086894989},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4484383165836334},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.43618881702423096},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.41176605224609375},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.3892388343811035},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3826275169849396},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3411043584346771},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33202630281448364},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.26378291845321655},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21916839480400085},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19119712710380554},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.16012361645698547},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1566375494003296}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9020317196846008},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.6563780307769775},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6541893482208252},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.5825543403625488},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.5207481384277344},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4759904146194458},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.456709086894989},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4484383165836334},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.43618881702423096},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.41176605224609375},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3892388343811035},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3826275169849396},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3411043584346771},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33202630281448364},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.26378291845321655},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21916839480400085},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19119712710380554},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.16012361645698547},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1566375494003296},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/s00034-013-9688-y","is_oa":false,"landing_page_url":"https://doi.org/10.1007/s00034-013-9688-y","pdf_url":null,"source":{"id":"https://openalex.org/S20109229","display_name":"Circuits Systems and Signal Processing","issn_l":"0278-081X","issn":["0278-081X","1531-5878"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320186","host_organization_name":"Birkh\u00e4user","host_organization_lineage":["https://openalex.org/P4310320186","https://openalex.org/P4310319900"],"host_organization_lineage_names":["Birkh\u00e4user","Springer Science+Business Media"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Circuits, Systems, and Signal Processing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1527137186","https://openalex.org/W1584008964","https://openalex.org/W1920855514","https://openalex.org/W1922693460","https://openalex.org/W1973127083","https://openalex.org/W1992170767","https://openalex.org/W2039157804","https://openalex.org/W2056365980","https://openalex.org/W2056456761","https://openalex.org/W2063907186","https://openalex.org/W2087512113","https://openalex.org/W2088115909","https://openalex.org/W2097193789","https://openalex.org/W2114603529","https://openalex.org/W2126388843","https://openalex.org/W2134067926","https://openalex.org/W2145585442","https://openalex.org/W2152037510","https://openalex.org/W2157101902","https://openalex.org/W2170265438","https://openalex.org/W2537611188","https://openalex.org/W3143002681","https://openalex.org/W4210673018","https://openalex.org/W4243164749","https://openalex.org/W6603040883","https://openalex.org/W6603951366"],"related_works":["https://openalex.org/W2489015823","https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W2516396101","https://openalex.org/W2049809742","https://openalex.org/W2584083726","https://openalex.org/W2584709885","https://openalex.org/W2903539032","https://openalex.org/W2027242255"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}