{"id":"https://openalex.org/W1604976820","doi":"https://doi.org/10.1007/bfb0055266","title":"A novel field programmable gate array architecture for high speed arithmetic processing","display_name":"A novel field programmable gate array architecture for high speed arithmetic processing","publication_year":1998,"publication_date":"1998-01-01","ids":{"openalex":"https://openalex.org/W1604976820","doi":"https://doi.org/10.1007/bfb0055266","mag":"1604976820"},"language":"en","primary_location":{"id":"doi:10.1007/bfb0055266","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bfb0055266","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009772492","display_name":"Nory Miller","orcid":null},"institutions":[{"id":"https://openalex.org/I79619799","display_name":"University of Birmingham","ror":"https://ror.org/03angcq70","country_code":"GB","type":"education","lineage":["https://openalex.org/I79619799"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"N. L. Miller","raw_affiliation_strings":["Digital Systems & Vision Processing Group, University of Birmingham, School of Electrical & Electronic Engineering, B15 2TT, Edgbaston, Birmingham, UK","University of Birmingham, School of Electrical & Electronic Engineering"],"affiliations":[{"raw_affiliation_string":"Digital Systems & Vision Processing Group, University of Birmingham, School of Electrical & Electronic Engineering, B15 2TT, Edgbaston, Birmingham, UK","institution_ids":["https://openalex.org/I79619799"]},{"raw_affiliation_string":"University of Birmingham, School of Electrical & Electronic Engineering","institution_ids":["https://openalex.org/I79619799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109213028","display_name":"S.F. Quigley","orcid":null},"institutions":[{"id":"https://openalex.org/I79619799","display_name":"University of Birmingham","ror":"https://ror.org/03angcq70","country_code":"GB","type":"education","lineage":["https://openalex.org/I79619799"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"S. F. Quigley","raw_affiliation_strings":["Digital Systems & Vision Processing Group, University of Birmingham, School of Electrical & Electronic Engineering, B15 2TT, Edgbaston, Birmingham, UK","University of Birmingham, School of Electrical & Electronic Engineering"],"affiliations":[{"raw_affiliation_string":"Digital Systems & Vision Processing Group, University of Birmingham, School of Electrical & Electronic Engineering, B15 2TT, Edgbaston, Birmingham, UK","institution_ids":["https://openalex.org/I79619799"]},{"raw_affiliation_string":"University of Birmingham, School of Electrical & Electronic Engineering","institution_ids":["https://openalex.org/I79619799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5009772492"],"corresponding_institution_ids":["https://openalex.org/I79619799"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.20640301,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"386","last_page":"390"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8690004348754883},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6539390683174133},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5784751176834106},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.546509861946106},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5449129939079285},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.533885657787323},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4837394058704376},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4598027765750885},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.437186062335968},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4199817478656769},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4135544002056122},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32471346855163574},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.26777881383895874},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.26347243785858154},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12539124488830566},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.103272944688797},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.09048402309417725},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0563187301158905}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8690004348754883},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6539390683174133},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5784751176834106},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.546509861946106},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5449129939079285},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.533885657787323},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4837394058704376},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4598027765750885},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.437186062335968},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4199817478656769},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4135544002056122},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32471346855163574},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.26777881383895874},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.26347243785858154},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12539124488830566},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.103272944688797},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.09048402309417725},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0563187301158905},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bfb0055266","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bfb0055266","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4000000059604645,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1600600529","https://openalex.org/W2011297197","https://openalex.org/W2073075989","https://openalex.org/W2126255765"],"related_works":["https://openalex.org/W2466591189","https://openalex.org/W594316872","https://openalex.org/W1608572506","https://openalex.org/W2491784425","https://openalex.org/W3047339307","https://openalex.org/W2123189957","https://openalex.org/W3034517114","https://openalex.org/W2794692675","https://openalex.org/W3139819943","https://openalex.org/W629811444"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}